fatslob-:O said:
Scoobes said:
Surely there will be ways around this? It's what engineers do, right? They hit a brick wall, then invent a bulldozer.
How's research into 3D integrated circuits going? Couldn't this be a possible way around the problem of costs not decreasing significantly with further die shrinks? |
Even engineers and scientists have their limits ... Once Moore's Law arrives at an end it will hit a lot of industries really hard. The chip manufacturing industry is headed towards for a dead end or a long stand still. Even if we can surpass economical limits of feature size reduction there will always be physical limits that will ultimately stop us from proceding any further to the next node.
The research on stacked dies is going well at the moment. Altera has announced support for stacked memory solutions in their Stratix 10 and their recently released Arria 10 FPGAs. Die stacking is also hardly the solution to cost reduction as there would only be noticeable savings towards stacking smaller dies since these chips have high yields to accomodate for that kind of expense.
There really are no solutions for cost effective die shrinking other than transitioning to a new and better scanner and if EUV does get adopted the industry will have only avoided the inevitable for another 5 yeas at most.
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This may be a stupid question, but won't we be able to design smaller chips with higher yields if we can multi-stack? For instance, could you design the equivalent of a Titan GPU in transistor count but on two different layers, theoretically halving the transistors per wafer and improving yield (per layer)? I guess each layer/wafer would need to be QA tested seperately for that to work.
Or am I pretty far off base? This isn't a topic I've read much on.
Also, saw this earlier. It sounds like AMD PR with a couple of silly statements from the writer thrown in, but it seems relevant to the thread:
http://www.tomshardware.com/news/amd-apu-efficient-goal-moore,27099.html
Wow. AMD is ambitious.
Rather than announcing a new product, AMD has announced a new target called the 25X20. The idea behind it is APU efficiency.
So what exactly does the target entail? Well, AMD wants its APUs to be 25 times more efficient by the year 2020. The company indicated that over the last six years (an equal time period from today till 2020), its products became about ten times more efficient. The company also recognized that if such improvements take place, the company will be outpacing Moore's law by about 70 percent.
"Creating differentiated low-power products is a key element of our business strategy, with an attending relentless focus on energy efficiency," said Papermaster. "Through APU architectural enhancements and intelligent power efficient techniques, our customers can expect to see us dramatically improve the energy efficiency of our processors during the next several years. Setting a goal to improve the energy efficiency of our processors 25 times by 2020 is a measure of our commitment and confidence in our approach."
Of course, energy efficiency should not be confused with power consumption. It is very unreasonable to expect the APUs to use 25 times less power six years from now. Instead, they will become more powerful and consume less energy while doing so, improving the overall performance per watt. That is AMD's target -- improving performance per watt by a multiple of 25.
Now, we're not exactly sure about how AMD intends to outpace science, though the company does mention three core foci: heterogeneous computing and power optimization, where the GPU and CPU aboard the APU work more closely together; intelligent real-time power management; and future innovation in power efficiency. In short, not only will the company shrink the transistors to make for more efficient APUs, it'll also work on newer architectures and better power management, and maybe even more.
There has to be something that gives AMD the confidence to make an announcement as ambitious as this… We're curious what it is that AMD has up its sleeve.
