| Scoobes said: Surely there will be ways around this? It's what engineers do, right? They hit a brick wall, then invent a bulldozer. How's research into 3D integrated circuits going? Couldn't this be a possible way around the problem of costs not decreasing significantly with further die shrinks? |
Even engineers and scientists have their limits ... Once Moore's Law arrives at an end it will hit a lot of industries really hard. The chip manufacturing industry is headed towards for a dead end or a long stand still. Even if we can surpass economical limits of feature size reduction there will always be physical limits that will ultimately stop us from proceding any further to the next node.
The research on stacked dies is going well at the moment. Altera has announced support for stacked memory solutions in their Stratix 10 and their recently released Arria 10 FPGAs. Die stacking is also hardly the solution to cost reduction as there would only be noticeable savings towards stacking smaller dies since these chips have high yields to accomodate for that kind of expense.
There really are no solutions for cost effective die shrinking other than transitioning to a new and better scanner and if EUV does get adopted the industry will have only avoided the inevitable for another 5 yeas at most.
