The intent to implement volatile cache tag lines prevents both of the caches from constantly flushing the caches to keep a consistent view of memory and instead is used to just update each others caches.

Edit: It appears that nothing is exactly specified about the black line and it doesn't even list bandwidth stats and such. It could be just an error on the slide. 

Edit 2: What ever that black line is I don't think its some generic bus to pass around data as other parts of the slide makes this obvious that to denote whether or not its some bus the rest of them have the specified bandwidth's listed.

Thanks, understood.  So at this time no knows what that black line means besides the CPU has access to the ESRAM.  

I wouldn't go as far as to say it has access to since it didn't list a bandwidth but what ever it is its probably not a bus meaning it probably can't access esram.              
Edit: Even if that black line could access the esram how would it deal with data collisions because at some point once the gpu and cpu access the same data the program data will not remain safe anymore and errors will start to occur because of memory overwrites.

So the guy made a basic assumption error thinking that in the diagram 4x64 bit => 4 x 68GB/s but in reality 4x64bit => 68GB/s. I can somewhat see how that assumption error can be made if you don't have a clue how X bits translates to Y GB/s. So each "pipe" coming from each 2GB DDR3 unit is running at 68/4 GB/s or 16GB/s right?

A noob error, but one any noob can make. I would make that error, which is why I don't start threads trying to explain how the tech works.

Just so I am clear on the diagram, it says that the GPU, CPU, Special Processors All share memory via the MMU which has a synchronized page table.  From my understanding, I thought that is what HUMA is.  Is there something wrong with that description.

hUMA is all about utilizing the gpu and to do that AMD believes that sharing data is the key and the MMU is just used to access physical memory non coherently meaning each special processor has its own partitioned memory.                                      
Edit: hUMA right now means being able to pass cpu pointers to gpus and also being cache coherent but once that is over hUMA will have another goal in mind .      

From my own research in the area, a synchronized page table is what you need to keep coherency between the CPU, GPU and those special processors.  I believe we have to separate buzz word from functionality.  The setup MS has is not HUMA defined by AMD but it appears to have a HUMA type of Arch since it states coherency between the different processors.  A paging table is used so that the CPU, GPU or those special processors would not need to see each other memory but instead that info will be referenced within the paging table, which from the slide all have access to.

Another question you need to ask your self is that why the cpu isn't directly linked to the gpu mmu which leads me to believe that the cpu isn't able to give its pointer directly to the gpu which means having a unified adressable memory is impossible without memory translations.
                                                                           Edit: one of the two current goals of hUMA is the the gpu being able to use the cpu pointer directly. Page tables on gpu mmu only helps to respond its own virtual memory.

I believe there is a reason why the CPU and GPU are not directly linked and it has to do with the Hyper V setup MS created for the X1.

Reading more into MS design, I am of the opinion that their setup is more complex than AMD HUMA design because all processors have a hardware page table which they share.  Because of this, there need not be any read access to to each individual processor memory which would delay process time(Basically what HUMA tries to avoid).  One area that probably really takes advantage of this setup outside of just the CPU, GPU is the Hyper VMs MS is using.  In order to make sure the VMs run as fast as possible, having a Hardware page table for all the processors helps to maintain each OS separation from each other and stepping on each other memory.  Also this setup helps maintain coherency between all the processors which would be used within a Hyper V setup which is more complex than just allowing direct access to the CPU and GPU.  Just my theory but I do have some links I might share later on once I wrap my head around the whole thing.

I have an imaginary friend. We spend alot of time together. We do things.