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fatslob-:O on 16 September 2013
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ethomaz said:

fatslob-:O said:

Hmmm the black line does not directly connect to the cpu cache but rather if you look at the diagram it connects to a the bus of a cache which leads me to believe it exactly doesn't snoop the cpu's L1 and L2 cache but hUMA also requires things like volatile cache tag lines to mark what has changed from either sides of a cache so that a coherent cache bus can send the changes to either the cpu or gpu cache.

Exactly... the difference between hUMA and NUMA is that the first you have the cache refresh in both (CPU and GPU) all the time (coherent)... in NUMA you need to refresh the cache before access the other memory (non-coherent), CPU need to update the CPU-cache to see all the latest GPU memory and GPU need to update the GPU-cache to see all the latest CPU memory.


The intent to implement volatile cache tag lines prevents both of the caches from constantly flushing the caches to keep a consistent view of memory and instead is used to just update each others caches.

Edit: It appears that nothing is exactly specified about the black line and it doesn't even list bandwidth stats and such. It could be just an error on the slide. 

Edit 2: What ever that black line is I don't think its some generic bus to pass around data as other parts of the slide makes this obvious that to denote whether or not its some bus the rest of them have the specified bandwidth's listed.