fatslob-:O said:
Machiavellian said:
fatslob-:O said:
Machiavellian said:
ethomaz said:
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Machiavellian said:
Since that black line connects directly with the ESRAM, would that not mean that the ESRAM is probably used as a cache for the GPU and thus the CPU can read its contents making the system HUMA capable.
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Every APU can do that and it is not hUMA... hUMA means you don't need to refresh the CPU-cache to see how the GPU mem is being used... in any APU I can access the GPU memory but I need to refresh my cache table before that.
That's what mean coehent... you don't need to update your cache table to see the latest updates made by GPU (or vice-versa).
So no... the CPU can access the eSRAM without hUMA... what will make it hUMA is if the CPU-cache table coherent with GPU-cache table for eSRAM... if you need to do a refresh everythime you will access the eSRAM then it is not hUMA... in fact it is NUMA.
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Thanks, understood. So at this time no knows what that black line means besides the CPU has access to the ESRAM.
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I wouldn't go as far as to say it has access to since it didn't list a bandwidth but what ever it is its probably not a bus meaning it probably can't access esram.
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Just so I am clear on the diagram, it says that the GPU, CPU, Special Processors All share memory via the MMU which has a synchronized page table. From my understanding, I thought that is what HUMA is. Is there something wrong with that description.
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hUMA is all about utilizing the gpu and to do that AMD believes that sharing data is the key and the MMU is just used to access physical memory non coherently meaning each special processor has its own partitioned memory.
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From my own research in the area, a synchronized page table is what you need to keep coherency between the CPU, GPU and those special processors. I believe we have to separate buzz word from functionality. The setup MS has is not HUMA defined by AMD but it appears to have a HUMA type of Arch since it states coherency between the different processors. A paging table is used so that the CPU, GPU or those special processors would not need to see each other memory but instead that info will be referenced within the paging table, which from the slide all have access to.
