fatslob-:O said:
Machiavellian said:
fatslob-:O said:
Machiavellian said:
fatslob-:O said:
Machiavellian said:
ethomaz said:
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Machiavellian said:
Since that black line connects directly with the ESRAM, would that not mean that the ESRAM is probably used as a cache for the GPU and thus the CPU can read its contents making the system HUMA capable.
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Every APU can do that and it is not hUMA... hUMA means you don't need to refresh the CPU-cache to see how the GPU mem is being used... in any APU I can access the GPU memory but I need to refresh my cache table before that.
That's what mean coehent... you don't need to update your cache table to see the latest updates made by GPU (or vice-versa).
So no... the CPU can access the eSRAM without hUMA... what will make it hUMA is if the CPU-cache table coherent with GPU-cache table for eSRAM... if you need to do a refresh everythime you will access the eSRAM then it is not hUMA... in fact it is NUMA.
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Thanks, understood. So at this time no knows what that black line means besides the CPU has access to the ESRAM.
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I wouldn't go as far as to say it has access to since it didn't list a bandwidth but what ever it is its probably not a bus meaning it probably can't access esram.
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Just so I am clear on the diagram, it says that the GPU, CPU, Special Processors All share memory via the MMU which has a synchronized page table. From my understanding, I thought that is what HUMA is. Is there something wrong with that description.
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hUMA is all about utilizing the gpu and to do that AMD believes that sharing data is the key and the MMU is just used to access physical memory non coherently meaning each special processor has its own partitioned memory.
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From my own research in the area, a synchronized page table is what you need to keep coherency between the CPU, GPU and those special processors. I believe we have to separate buzz word from functionality. The setup MS has is not HUMA defined by AMD but it appears to have a HUMA type of Arch since it states coherency between the different processors. A paging table is used so that the CPU, GPU or those special processors would not need to see each other memory but instead that info will be referenced within the paging table, which from the slide all have access to.
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Another question you need to ask your self is that why the cpu isn't directly linked to the gpu mmu which leads me to believe that the cpu isn't able to give its pointer directly to the gpu which means having a unified adressable memory is impossible without memory translations.
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I believe there is a reason why the CPU and GPU are not directly linked and it has to do with the Hyper V setup MS created for the X1.
Reading more into MS design, I am of the opinion that their setup is more complex than AMD HUMA design because all processors have a hardware page table which they share. Because of this, there need not be any read access to to each individual processor memory which would delay process time(Basically what HUMA tries to avoid). One area that probably really takes advantage of this setup outside of just the CPU, GPU is the Hyper VMs MS is using. In order to make sure the VMs run as fast as possible, having a Hardware page table for all the processors helps to maintain each OS separation from each other and stepping on each other memory. Also this setup helps maintain coherency between all the processors which would be used within a Hyper V setup which is more complex than just allowing direct access to the CPU and GPU. Just my theory but I do have some links I might share later on once I wrap my head around the whole thing.
