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zeldaring on 15 September 2023
sc94597 said:
Yeah that is what prompted the discussion here, yesterday, September 14th. |
what you think of this
It's sort of true, but also not really that relevant to the comparison. Partly because we're comparing between different foundries. TSMC's more mature nodes very likely have better yields than their newer nodes, but there's no particular guarantee that an older Samsung node has better yields than a newer TSMC node. TSMC's 5nm node family (which includes 4N) reportedly achieved very good yields at an early stage, and now has been used in shipping products for over 3 years, so is relatively mature in any case.
Secondly, yields are inversely proportional to die size, and if you are comparing yields of the same chip between the two processes, this is probably going to be the bigger factor. In this case, we're talking about the same chip either way. We know it's got 8 CPU cores, 12 Ampere SMs, and has assorted other coprocessors, interfaces, etc., and these things are going to take up the same number of transistors whether it's on TSMC 4N or Samsung 8N, so it would have to be a much bigger chip on 8N.
For the sake of argument, let's say it's a 10 billion transistor chip, just for a round number. On Samsung 8N, Nvidia was getting a transistor density of around 45.6 million transistors per mm², which would indicate a die size of 219.3mm². On TSMC 4N, Ada chips are coming in at about 121.1 mT/mm², which would give a die size of 82.6mm². The 4N version of the chip is obviously much smaller.
Now let's talk about yields. You may see articles claiming that a process has "70% yields" or "90% yields", which are irrelevant if you don't know the size of the die. A 70% yield on an 800mm² chip would be incredible, whereas a 90% yield on a 20mm² chip would be below-par. The actual measurement of yields* is defect density, which is a measure of how many defects you have per unit of die area. Typically this is measured in defects per cm². This Anandtech article from before TSMC 5nm chips hit the market indicated they were operating at a defect density of about 0.1 per cm², and showed yields had improved more quickly than their previous nodes.
There's a little maths involved to calculate the yield of a chip from a die size and defect density:
Yield = (1 - DefectRate)^DieSize
Where both the defect rate and die size are measured in the same units (in this case we want to convert them to cm²).
Let's assume for a second that both Samsung 8N and TSMC 4N have the same 0.1 per cm² defect rate. Using the die sizes above, and the formula for yield, we get a yield of 79% for 8N and 92% for 4N. That's the difference the die size makes. Even if Samsung had half the defect rate, at 0.05, it would still only manage 89% yields. Realistically, yields have almost certainly improved for TSMC's 5nm class of process in the 3 years since that article, so I wouldn't be surprised if we're at around 95% yields on 4N for T239.
* There's actually also a second, completely separate measurement of yields, called parametric yields. The parametric yields are considered low when chips, although functional, aren't able to hit the required clock speeds, or require too high a voltage to do so. This is quite a different problem, as much to do with chipmakers expectations as to do with the actual process, but clearly wouldn't be a problem for 4N, as it would produce chips capable of much higher clocks at much lower voltages than 8N could.
Secondly, yields are inversely proportional to die size, and if you are comparing yields of the same chip between the two processes, this is probably going to be the bigger factor. In this case, we're talking about the same chip either way. We know it's got 8 CPU cores, 12 Ampere SMs, and has assorted other coprocessors, interfaces, etc., and these things are going to take up the same number of transistors whether it's on TSMC 4N or Samsung 8N, so it would have to be a much bigger chip on 8N.
For the sake of argument, let's say it's a 10 billion transistor chip, just for a round number. On Samsung 8N, Nvidia was getting a transistor density of around 45.6 million transistors per mm², which would indicate a die size of 219.3mm². On TSMC 4N, Ada chips are coming in at about 121.1 mT/mm², which would give a die size of 82.6mm². The 4N version of the chip is obviously much smaller.
Now let's talk about yields. You may see articles claiming that a process has "70% yields" or "90% yields", which are irrelevant if you don't know the size of the die. A 70% yield on an 800mm² chip would be incredible, whereas a 90% yield on a 20mm² chip would be below-par. The actual measurement of yields* is defect density, which is a measure of how many defects you have per unit of die area. Typically this is measured in defects per cm². This Anandtech article from before TSMC 5nm chips hit the market indicated they were operating at a defect density of about 0.1 per cm², and showed yields had improved more quickly than their previous nodes.
There's a little maths involved to calculate the yield of a chip from a die size and defect density:
Yield = (1 - DefectRate)^DieSize
Where both the defect rate and die size are measured in the same units (in this case we want to convert them to cm²).
Let's assume for a second that both Samsung 8N and TSMC 4N have the same 0.1 per cm² defect rate. Using the die sizes above, and the formula for yield, we get a yield of 79% for 8N and 92% for 4N. That's the difference the die size makes. Even if Samsung had half the defect rate, at 0.05, it would still only manage 89% yields. Realistically, yields have almost certainly improved for TSMC's 5nm class of process in the 3 years since that article, so I wouldn't be surprised if we're at around 95% yields on 4N for T239.
* There's actually also a second, completely separate measurement of yields, called parametric yields. The parametric yields are considered low when chips, although functional, aren't able to hit the required clock speeds, or require too high a voltage to do so. This is quite a different problem, as much to do with chipmakers expectations as to do with the actual process, but clearly wouldn't be a problem for 4N, as it would produce chips capable of much higher clocks at much lower voltages than 8N could.
