If you have a car and a boat, those will performance much better than a boatcar. Similarly 3xCELLs was like nothing compared to RSX graphical abilities.

1) not necessarily true, just look at the performance gain achieved by amd when the moved the memory controller on chip in their days of obvious superiority.

Ability to perform at what? Maybe I want to drive through the everglades, boatcar would win hands down.

Anyways the modern GPUs are all turning into boatcars anyhow.

Everyone is IBM. Big Blue domination.

They are basing it off the x86 P1 processor. Since its got an X86 lineage I doubt they will be hurting for a compiler.

The Itanic was a completely new architecture, this is x86 based.

This isn't a GPGPU application. Its straight up GPU work here.

Larrabee can hide the latency of incoherent reads as it uses L1 to accumulate the data before the thread resumes.

It seems to me that a core is defined as logic+L1+L2. Each L2 is only used by its core. Cores can only access foreign L2s under the cache-coherency protocol, which is effectively a request to fetch data to make a local copy

link

Going X86 for the CPU would make them extremely happy. The time they save on the CPU coding they could easily spend getting up to speed on the GPU side. It would make porting games between the PC/Console extremely easy.

Larrabee has a CPU architecture but its designed mainly as a GPU and it has fixed funtion hardware for that purpose. Thats something which the CELL lacks.

I think you may be confusing the microarchitecture and the ISA http://en.wikipedia.org/wiki/Instruction_set. The cell uses the POWER ISA, does that mean it can use the same compiler as the xenon which also uses the POWER ISA?

For MS??? HA!!

Xbox came in 2001, 360 came in 2005. That's not too early at all when I think of the fact that it's MS...

What you just described (and the link) is a fancy way of saying it's not really cache-coherent. The cell literature actually tries the same trick.