>> So which is better?

Xenon, counter to most people's intuition, I suspect will run CRCW algorithms faster. That is, if each core is reading and writing to data that no other core is going to read or write to (located in it's own cache, once it has to look outside there are going to be bus congestion issues). As soon as there is any kind of data sharing a given core has to tell all the others to stop what they are doing so they can synchronize. Otherwise, the copy of the data a given core has could be out of date.

The SPUs were designed with interconnects in mind, so they can communicate with each other quickly and with minimal congestion due to their network topology. This lends them to EREW algorithms, that is algorithms which require locking and algorithms with a runtime storage that can fit in the caches of all the SPEs (remember they can access each others caches very quickly).

>> And what does it mean the Cell has a PPE?

Beside the hardware bootstraping stuff which isn't really relavent, the PPE functions as a normal-ish POWER core with only a slightly reduced instruction set from the HPC POWER line. The SPEs use a RISC instruction set and eliminate OOE (out of order execution) inorder to take SRAM which is normally dedicated to instruction translation and pooling (remember the assembly instructions you see in a CISC machine have to be translated by the chip at runtime to the real instructions the chip can understand) to use as more highspeed cache and a more sophisticated DMA controller.

So the difference comes down to PPE optimizes the order of instruction execution better and the SPEs optimize the order of memory IO better.

>> And who the hell knows what your talking about besides whoever knows what your talking about?

Well, there are a few people here I think who do. If you need some jargon explained I'd be happy to try to explain. Do you understand C?

>> And since it said that the Xenon's three PPE's under a single DIE which are modified versions of the one >> in the Cell... what would the difference be?

The difference between the PPEs is minimal, MS got IBM to change ALTIVEC a bit, but the difference is minimal.

Squilliam said: @Alephnul, I've heard of that exact frustration with the PS3s compiler before. Is that still the case? Anyway, so you're going to spill the beans on the differences/similarities between the VMX units in the Xbox 360 to the SP units in the Cell?

I forgot to mention, this isn't a problem with the IBM compiler, but compilers in general. That was the part of the point of using the intel example. Even compilers using full Fourier-Motzkin variable elimination will not be able to vectorize those loops. This is a hot area in compilers right now, if you can figure out a way to do it there will be long lines of people waiting to throw money at you. This is an issue for any architecture with SIMD instructions.

No C++ there, only C. There are C++ instrinsics, but OO programming wreaks havok on data alignment and for whatever reason the C++ instrinsics run ~10 slower in our tests than the C ones which map directly to the assembly ops except in a few cases.

Ah yes, one of the greatest processors of all time.

You can use any language that has a compiler that will run on a POSIX system. The game developer libraries are C++, only inner loops need to run fast. The HPC people write alot of stuff in FORTRAN or HPF still as the BLAS libraries are all in FORTRAN and it's actually faster than C under some circumstances. Theres also a people doing stuff in various functional languages like ERLANGEN as the lack of side-effects is supposed to ease the development of parallel code.

I learn a little C# but not much....