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Forums - Nintendo Discussion - FAST Racing NEO powered by 2nd generation engine for Wii U supports and uses 4k-8k textures

Wyrdness said:
fatslob-:O said:

Denial much ? 


See at least you're now acknowledging where you're going wrong now it's a start.

You still denying that the WII U has 12.8 GB/s ? 



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fatslob-:O said:
curl-6 said:

A Treyarch dev on the official forums said it was harder to work with IW's code than Treyarch's.

That's extremely strange since the WII U is easier to code for than the PS360! 

But devs have 7-8 years of experience wih PS3/360 and as a result are intimately familiar with them and have very mature dev tools, whereas Wii U is comparatively new to them. Then there's the fact that they didn't expect the Wii U version to sell well and hence likely didn't invest much in the port.



curl-6 said:
fatslob-:O said:
curl-6 said:

A Treyarch dev on the official forums said it was harder to work with IW's code than Treyarch's.

That's extremely strange since the WII U is easier to code for than the PS360! 

But devs have 7-8 years of experience wih PS3/360 and as a result are intimately familiar with them and have very mature dev tools, whereas Wii U is comparatively new to them. Then there's the fact that they didn't expect the Wii U version to sell well and hence likely didn't invest much in the port.

Agreed with the fact that they likely didn't spend too much time with it. 



well, i would like to think the way you do, but 2ghz for the edram is unlikely, nec reported 40nm edra at a maxiu of 800mhz in 2007

http://www.techpowerup.com/44979/nec-introduces-40nm-embedded-dram.html

"

Tuesday, November 20th 2007

NEC Introduces 40nm Embedded DRAM

Jimmy 2004

NEC Electronics Corporation today introduced two new technologies for the manufacture of 40-nanometer (nm) system-on-chip (SoC) devices with embedded dynamic random access memory (eDRAM). The UX8GD eDRAM technology boasts clock speeds up to 800 megahertz and low operating power, making it optimal for use in consumer electronics products such as digital video cameras and game consoles. The UX8LD eDRAM technology features low leakage-current levels that reduce power consumption by as much two-thirds compared to equivalent SRAM, making it ideal for use in mobile handsets and other portable devices that require low standby power.

"

 

besides, i am not sure if the edram can have more clock speed than the gpu clock speed. i mean, just look at gamecube, the main 1tsram had about 324mhz of speed, yet the mebedded 1tsram in teh gpu had to downclock the sp'eed to the flipper 162mhz,so its pretty unlikely what you say , unless you have a good example to tell otherwise

 

here, this should be interesting, going back to the past

http://www.segatech.com/gamecube/overview/

 

 

 

Specifications

First released by Nintendo at Nintendo's Spaceworld on August 24th, 2000 in Tokyo, Japan. New specs announced by Nintendo on it's website on May 15th, 2001, during the 2001 E3 show in LA. "Gekko" CPU upgraded from 400 MHz to 485 MHz, and "Flipper" GPU downgraded from 202.5 MHz to 162 MHz. 

Texture Cache 

Here is any interesting article from AsiaBizTech that provides some information on the number of simultaneous accesses that can occur with the texture cache:

Parallel Processing of 32 Access Transactions

The Flipper LSI has two units of the 1T-SRAM memory integrated, namely, 2.1MB for a frame-buffer and Z-buffer and 1MB for a texture cache. NEC Corp. manufactures the LSI. 

It was necessary to enhance random access performance of 1T-SRAM applied to a texture cache which will be frequently accessed, thus making it faster than that used for the frame-buffer and Z-buffer. To meet this need, the entire bank was divided into 512 pieces. Fu-Chien Hsu, chairman and CEO of MoSys said, "Of those component banks, 32 banks can be accessed simultaneously." On the other hand, the frame and Z buffer was designed to have 128 banks, since there was no strong need to offer high operation with this buffer. 

The main memory of the Gamecube consists of two sets of 96Mbits 1T-SRAM. As it can drive a 64-bit data-bus at 400MHz*, the machine transfers data at up to 3.2GB* per second, which is the same rate the PlayStation2 has achieved through the Direct Rambus interface consisting of two channels.

However, latency on random access to the main memory is slower than that of the 1T-SRAM being embedded in the Flipper LSI, which results from a configuration of the main memory being externally attached. Nonetheless, the memory access is completed in less than 10ns, sufficiently faster than multi-purpose DRAM.

**Note: Data bus transfer is now 2.6 GB/sec due to revised specs, and the external 64-bit data-bus runs at 324 MHz now.

 

More info on the internal bandwidth of the caches from here:

Both internal memory buffers have a sustained latency of under 5 nanoseconds. The frame and z-buffer memory is capable of 7.68 Gbytes/second of bandwidth. The texture buffer boasts an even faster bandwidth of 10.4 Gbytes/s because it's divided into 32 independent macros, each 16 bits wide for a total I/O of 512 bits. This gives each macro its own address bus, so that all 32 macros can be accessed simultaneously, said Mark-Eric Jones, vice president of marketing for Mosys. 
"


fatslob-:O said:

You still denying that the WII U has 12.8 GB/s ? 


Point to where I mention what the U has? As well as getting schooled on the formula for bandwidth where you a self proclaimed tech expert was given clues you also can't read comprehensively, how interesting, don't they teach tech experts how to read and write or are you left to your own devices or is it just a situation where you are a special case?



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megafenix said:

well, i would like to think the way you do, but 2ghz for the edram is unlikely, nec reported 40nm edra at a maxiu of 800mhz in 2007


You're getting yourself confused.
I never stated the actuall eDRAM runs at 2ghz.



--::{PC Gaming Master Race}::--

These Wii U tech threads never fail to blow up into multi-hundred-post monsters, haha.



Wyrdness said:
fatslob-:O said:

You still denying that the WII U has 12.8 GB/s ? 


Point to where I mention what the U has? As well as getting schooled on the formula for bandwidth where you a self proclaimed tech expert was given clues you also can't read comprehensively, how interesting, don't they teach tech experts how to read and write or are you left to your own devices or is it just a situation where you are a special case?

Once again go school yourself on this issue. Take the argument up to pemalite if you don't agree with my assessment. 



Pemalite said:
megafenix said:

well, i would like to think the way you do, but 2ghz for the edram is unlikely, nec reported 40nm edra at a maxiu of 800mhz in 2007


You're getting yourself confused.
I never stated the actuall eDRAM runs at 2ghz.


sorry, is just that you got many things fixed here and there and i couoldnt get what you tried to mean

could you simplify it and make your point?

what has that abything to do with the wii u edra anyway?

gamecube was capable of 512 bits, why wii u would bottleneck with more than 1024bits anyway?

and isnt that like saying that nintendo selected the worse edram instead of the best likie the 8192bits or 4096bits?

isnt 1024 bits for wiiu edram to short compared to main ram ddr3 ram of 51.2gb/s of current standard pcs or even the xbox one esram of 200gb/s?



megafenix said:

well, i would like to think the way you do, but 2ghz for the edram is unlikely, nec reported 40nm edra at a maxiu of 800mhz in 2007

http://www.techpowerup.com/44979/nec-introduces-40nm-embedded-dram.html

"

Tuesday, November 20th 2007

NEC Introduces 40nm Embedded DRAM

Jimmy 2004

NEC Electronics Corporation today introduced two new technologies for the manufacture of 40-nanometer (nm) system-on-chip (SoC) devices with embedded dynamic random access memory (eDRAM). The UX8GD eDRAM technology boasts clock speeds up to 800 megahertz and low operating power, making it optimal for use in consumer electronics products such as digital video cameras and game consoles. The UX8LD eDRAM technology features low leakage-current levels that reduce power consumption by as much two-thirds compared to equivalent SRAM, making it ideal for use in mobile handsets and other portable devices that require low standby power.

"

 

besides, i am not sure if the edram can have more clock speed than the gpu clock speed. i mean, just look at gamecube, the main 1tsram had about 324mhz of speed, yet the mebedded 1tsram in teh gpu had to downclock the sp'eed to the flipper 162mhz,so its pretty unlikely what you say , unless you have a good example to tell otherwise

 

here, this should be interesting, going back to the past

http://www.segatech.com/gamecube/overview/

 

 

 

Specifications

First released by Nintendo at Nintendo's Spaceworld on August 24th, 2000 in Tokyo, Japan. New specs announced by Nintendo on it's website on May 15th, 2001, during the 2001 E3 show in LA. "Gekko" CPU upgraded from 400 MHz to 485 MHz, and "Flipper" GPU downgraded from 202.5 MHz to 162 MHz. 

Texture Cache 

Here is any interesting article from AsiaBizTech that provides some information on the number of simultaneous accesses that can occur with the texture cache:

Parallel Processing of 32 Access Transactions

The Flipper LSI has two units of the 1T-SRAM memory integrated, namely, 2.1MB for a frame-buffer and Z-buffer and 1MB for a texture cache. NEC Corp. manufactures the LSI. 

It was necessary to enhance random access performance of 1T-SRAM applied to a texture cache which will be frequently accessed, thus making it faster than that used for the frame-buffer and Z-buffer. To meet this need, the entire bank was divided into 512 pieces. Fu-Chien Hsu, chairman and CEO of MoSys said, "Of those component banks, 32 banks can be accessed simultaneously." On the other hand, the frame and Z buffer was designed to have 128 banks, since there was no strong need to offer high operation with this buffer. 

The main memory of the Gamecube consists of two sets of 96Mbits 1T-SRAM. As it can drive a 64-bit data-bus at 400MHz*, the machine transfers data at up to 3.2GB* per second, which is the same rate the PlayStation2 has achieved through the Direct Rambus interface consisting of two channels.

However, latency on random access to the main memory is slower than that of the 1T-SRAM being embedded in the Flipper LSI, which results from a configuration of the main memory being externally attached. Nonetheless, the memory access is completed in less than 10ns, sufficiently faster than multi-purpose DRAM.

**Note: Data bus transfer is now 2.6 GB/sec due to revised specs, and the external 64-bit data-bus runs at 324 MHz now.

 

More info on the internal bandwidth of the caches from here:

Both internal memory buffers have a sustained latency of under 5 nanoseconds. The frame and z-buffer memory is capable of 7.68 Gbytes/second of bandwidth. The texture buffer boasts an even faster bandwidth of 10.4 Gbytes/s because it's divided into 32 independent macros, each 16 bits wide for a total I/O of 512 bits. This gives each macro its own address bus, so that all 32 macros can be accessed simultaneously, said Mark-Eric Jones, vice president of marketing for Mosys. 
"

Gee you really don't know anything about tech, eh ? 

http://www.anandtech.com/show/6993/intel-iris-pro-5200-graphics-review-core-i74950hq-tested/3

Why does intel iris pro graphics have an eDRAM clock of 1.6 ghz ?! 

Something tells me you got yourself in this trap.