pt2
As for PS4, unexpected the possibility of remaining in gentle efficiency improvement is high vis-a-vis PS3. But SCE this time is planned, high cost not to be high performance, cost it is holding down, because it is seen that it is the directivity which can achieve performance. In order to hold down production cost, you stop the die/di size of the tip/chip small and if (CPU 100 square mm units), the Cell B.E. base being, increase of the number of CPU cores is estimated that you hold down. Perhaps, it probably will not increase dramatically from the present 8 cores. If we assume that process is 45nm, to store to the board in 100 square mm units, being many, the possibility of remaining in over ten cores is high. There is a possibility also operational frequency improving somewhat, but this does not rework big to the circuit design and architecture with does not rise to dramatic. When that happens, when you look at just CPU, live performance present 2.x time and, means not to rise that much dramatically. Though, with the waiting of feedback from [gemudeberotsupa], decision has not done yet concerning the number of CPU cores. It is not the case that it decides specification, there is a stage of research. But, the voice that is audible well SCE with PS4 takes the prudent route. By the way, concerning memory, it is not the memory like XDR DRAM where the adoption cases other than PS3 are few, it is said that the plan that has surfaced, general-purpose JEDEC (with subsystem of the American Electronics Industries Association EIA, the standardization group of the semiconductor) you use the memory of standard. This is for cost reduction. However, because with JEDEC DDR4 is cancelled in fact and becomes the divider correcting, with the phase of PS4 in fact, low only voltage edition DDR3 there are choices. However, stacking to the CPU die/di of DRAM memory or mounting inside the package examines also SCE.
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