lol, What the hell are you talking about ?

Neither the PS3, nor the XBOX360 or the Wii are x86 compatible, they are all PowerPC based.

The only recent x86 console thats worth mentioning, was the original XBOKS, so i don't think there are many x86 fanatics on this forum.

All this might come as a surprise to you!

p.s.

On Topic:

Regarding your CELL = Stream Processor discussion:

I haven't looked it up on wiki yet, but i'm on jetrii's side.

Why ? Cause he might know the difference between PowerPC and x86.

I know that...

I was talking about his statement that the "SPEs do not make sense anymore and IBM knows this"

that's the same kind of talk that people who want the status quo to remain the same, and keep the x86 alway's in the forefront of alway's being better than powerPC processor's.

an Elitist. if its not a GPU or a x86 than its not good for game's .

AND 

you agree with them is alright and ok but For me I tend to agree with one of the main designer's of what the chip is or is not:

DR. Hofstee explains what the Cell is:

ABSTRACT

This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the high-performance computing community. The Cell Broadband Engine^™ processor contains eight SPEs. The dual-issue, four-way single-instruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-FO4 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm² using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non-static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.

http://portal.acm.org/citation.cfm?id=1345059.1345063&coll=GUIDE&dl=GUIDE&CFID=63865659&CFTOKEN=31018906

now that's your opinion and while i respect that DR. Hofstee and I disagree with your take:

ABSTRACT

This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the high-performance computing community. The Cell Broadband Engine^™ processor contains eight SPEs. The dual-issue, four-way single-instruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-FO4 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm² using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non-static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.

http://portal.acm.org/citation.cfm?id=1345059.1345063&coll=GUIDE&dl=GUIDE&CFID=63865659&CFTOKEN=31018906

it does not matter if a GPU is geared toward the Graphic's and its faster than the Cell, which of course it is but on the same token the Cell processor is a streaming processor. that is a fact saying because a GPU may be faster does not take away the IDEA that the Cell is a GPU or that it also accelerates GPU function's.

the blunt truth of the matter is there are many on this board that like to claim what the Cell is in their Opinion, but Have little to near no experience with the Cell processor at all. and based on what other people have told them. who also may not have any experience at all have their IDEA what the Cell processor is .

No matter how flawed that PREDETERMINED IDEA MAY BE is they stick to it.

Now while i can respect some's Opinion on any matter , I also would like to think those same people can see other's Opinion's on the matter and not just dismiss their experience with something. That some on here may have.

That's not my opinion, that's a fact.  The Cell is NOT a stream processor.  Every cpu can process streaming data.  What you quoted has nothing to do with being a stream processor.

lol..so your saying DR. HOFSTEE IS WRONG?

THE GUY WHO HELP CREATE THE Cell Processor.

while i respect your Opinion, I tend to Agree with the Man who has spent the last 6 year's and more developing and creating the PROCESSOR.

And yes it does.

The SPE's in the Cell processor are in FACT stream processor's

here is a system architect at AMD states what a STREAMING PROCESSOR IS:

GPUs can act like a stream processor, but can go beyond a pure stream processor. The best working definition I think I can give is that a streaming processor must name all the elements it will access for each kernel invocation and it executes the same kernel across a stream of elements, often in a data parallel fashion (but a streaming processor can be serial). Others in the field might give you a slightly different variation, and if you ask a DSP guy, they will likely give you yet another definition. Wikipedia also has a version of this definition (http://en.wikipedia.org/wiki/Stream_processing) and (http://en.wikipedia.org/wiki/GPGPU). Other people view 'Stream Processing' as SIMD (much like a variant of vector processing, but without the 1 in 1 out restriction) as the DSP folks do where I tend to have a more relaxed view that it is SPMD.

When I say 'name elements' I mean that all the data can be localized before each kernel invocation or the data can be prefetched in time for execution. Where GPUs differ is that within the execution on an element you can calculate address to gather from, i.e. they can change what the access based on the data they are processing. Where things get really blury is that for GPUs to even run, you have to already localize data into the GPUs memory or into system addressable memory.

http://forum.beyond3d.com/showthread.php?t=38016

@joeorc:

i get the feeling you ran out of arguments and you are starting to quote the top 5 google hits out of desperation.

btw. It's annoying to see you quoting all these WALLS, plz learn to reply.

I thought that they just cut it?

ran out of argument's?

look, who ever you are which i do not know you at all, an this being the first instance between us in the forum, I am using FACT'S to back up my point in this debate. its not a wall of text just to be a wall of text. Its trying to teach some people on here what the Cell processor is an is not. If you would like to learn something keep reading if not, than that is you who is running out of argument's because if you have a valid reason why the Cell Processor is NOT a stream processor show me some information from say a PHD in computer science who happen's to be an expert in stream processor's. IF you cannot you may want to stay out of this one.