| Pemalite said: Really? From what I can tell AMD increased it to SIMD32 from SIMD16 on GCN and decreased wavefronts from 64 on GCN to 32. So no longer does it take 4 cycles for a wavefront to be pushed through on GCN, it's now 1 on Navi, if they have a SIMD64 mode, that is news to me. |
From their prior high level block layout diagrams, physically speaking it looks like 4xSIMD16 vector units but GCN's programming model (most important aspect) is actually SIMD64 because the hardware itself executes a 64-wide wavefront width due to it's single scalar unit which handles very important operations such as control flow, branching, and addressing ...
It'd be a disaster for GCN to have a SIMD16 programming model since 3/4ths of it's vector units would be deactivated when they couldn't be independently operated without separate scalar units to match. Now that RDNA has 2 scalar units per CU, it can support a SIMD32 programming model because of the corresponding ratio of scalar to vector units ...
I wonder if AMD are going to extend RDNA to have a separate scalar unit for each vector unit to support a true SIMD16 mode ...
Sure a driver's internal shader compiler could handle it but it'd be more juicier for a programmer to see the details and with next gen coming up it'd serve as another excuse for them to refactor their code to get the most out of it ...
