Pemalite said:
Eagle367 said:
I won't pretend to understand this jargon but isn't the switch speculated to be 16nm based on the pics leaked of its interior
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TSMC's 16nm process is basically 20nm with added Finfet, it still uses a 20nm BEOL, but does reduce the contacted poly pitch from 90nm to 80nm, but that is thanks to Finfet taking advantage of Z-height.
FEOL does get reduced compared to 20nm Planar, down to 16/14nm.
Planar = 2D Transistors.
Finfet = 3D Transistors. Essentially.
Density between TSMC's 16nm and 20nm process shouldn't be catastrophically different, most of the gains is thanks to Finfet, TSMC does use double patterning at 20nm and pitch splitting at 16nm finfet.
The main advantage with 16nm Finfet is that there should be less leakage, which should result in less electricity being wasted... Which means you can increase the chip size (More CUDA Cores) or you increase the clockspeed which gives you more performance for the same amount of power being consumed.
nVidia is building a 512 Cuda core based Tegra on 16nm Finfet (Volta/Xaviar), which should be possible on 20nm Planar, provided clocks are kept in check, but such a SoC would shine at 16nm Finfet and lower.
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wow I am lost for words. I seriously realized how people feel when I talk about physics with them. Wow i understood nothing
