Mnementh said:
Yes, that is true. But you can say similar for Nintendos CPU. We know it is no vanilla PowerPC, at least in Gamecube and then again in Wii they added additional instructions. Probably the same is true for WiiUs CPU. We don't know much besides that, but it is more than possible that they overworked pipelines and branch-prediction too. |
Yes, the gc PPC wasn't a vanilla PPC to begin with but it wasn't really a custom chip like Cell or Xenon. And reading https://fail0verflow.com/blog/2013/espresso.html tells me that there wasn't that much new stuff introduced to one of the cores itself.
And marcan also found out even more stuff of the cores: https://en.wikipedia.org/wiki/Wii_U_CPU
Broadway-based core architecture[14]
Three cores at 1.243125 GHz
Symmetric multiprocessing with MESI/MERSI support[15]
Each core can output up to 4 instructions per clock using superscalar parallelism.
32-bit integer unit
64-bit floating-point (or 2× 32-bit SIMD, often found under the denomination "paired singles")
A total of 3 MB of Level 2 cache in an unusual configuration.[16]
Core 0: 512 KB, core 1: 2 MB, core 2: 512 KB
4-6 stage pipeline
6 Execution Units per core (18 EUs total)
Die size: 4.74 mm × 5.85 mm = 27.73 mm2
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Especially the bolded:
Hector Martin
@marcan42
@DFaker no, it's just a 750. PPC750 can issue 3/cycle and retire 2/cycle. @dampflokfreund yes, three Broadways and more cache.
