| snowdog said: @freedquaker, you really need to stop thinking of Expresso being 3 Broadways duct-tapped together and Latte being 5 years old. Whilst Expresso is related to Broadway you should remember that Broadway is a single core processor unable to be pushed to 1GHz or more. Have you actually seen the die shots of both..? As with Latte, Expresso is a completely custom chip. Unfortunately the Latte discussion thread got locked on Gaf but I think the Expresso one is still going. You might want to give them a read and find out just how little we know about both chips. And it should also be noted that Broadway is a VERY capable CPU anyway. |
actually, can just be based, but cant be just a broadway cause 750 were not made for multicore and thats a harwdare problem not software, we can see that here at ibm
https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/291C8D0EF3EAEC1687256B72005C745C#10
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1.10 Can these processors be used in SMP designs?
750CXe/FX/GX (and other 750 processors) can work in an SMP environment; it just takes extra work in the software and OS kernel, and there will be extra bus traffic. The fundamental problem is that the cache management instructions (in particular dcbf, dcbst, dcbi) only operate on the local CPU's caches by default; they are not broadcast on the 60x bus for other processors to see unless ABE is set. Other SMP-capable PowerPC implementations broadcast these operations so they act on all caches in the system. In addition, the 750 family doesn't broadcast TLB invalidations, and it doesn't snoop instructions on the bus, so it wouldn't pick up these other operations even if they were broadcast.So using these processors in an SMP design would require having the software and OS ensure that each CPU in the system performed each of these tasks every time it needed to be done by one of the CPUs.
Basically, SMP operation can be done, but it will require a lot of software overhead, which may impact overall performance for both the kernel and user application code. As with other performance characteristics, it will depend heavily on the application.We have no quantitative data, but if two MEI processors are used without consideration to how tasks are partitioned between the processors, there will be a penalty due to shared data that will be continuously flushed out of one processor when the other processor needs it, along with the maintenance problems of tlbie and dcb operations. If tasks can be partitioned such that there is very little data sharing, then there will be correspondingly very little overhead for maintaining coherency between the two processors.
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MEI processors are not prepared for multicore, you need a MESI OR MERSI coherent ptocessor for that, so wither nintendo made lots of changes on the cpu for multicore or just pick another processor and make the necessary changes to understand understand the broadway code
