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Kaizar on 11 August 2013
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the-pi-guy said:
joeorc said:
the-pi-guy said:
Kaizar said:

 

It seems like the PS Vita has everything going against it, from 140 million polygons VS. 160 million polygons to a maximum of 40 shader ores VS. a minimum of 50 shader cores, to each handheld having a 4-core target up to 1 GHz CPU withthe ARM11 focusing so much of synthesis or whatever that it gives it an advantage over other CPU, unless you use ARM11 on a 3rd party device which would just cause a whole bunch of unknown bugs & glitches you will never find (so ARM11 can only be use in a Nintendo device, but gives it an advantage over all other CPUs when it's in a 1st party device).

The PS Vita just seems to have too much going against it across the board, including photo taking & video recording & Augmented Reality.

 

I'd love to see some sources for these claims.   

do not even bother, many of the People who know Arm Cortex based processor's and GPU's that go into the SOC's have tried to explain his Myth of the 3DS being anywhere near the hardware performance of the PSVita is not only pie in the sky hope, but its downright wrong in what he keep's posting, the fact that he keep's posting this when Arm Holding's info on the SOC's shows just how wrong he is, show's he is not interested in learning about the hardware, he just wants to make claims that are no where near being truthful.

Thanks, I'll try to keep that in mind.  :)


Well here's what I have found so far about the specs. The 3DS CPU seems to have an advantage over all other 4-core 1 GHz CPUs when used on a 1st party device like the 3DS, but if you use it on a 3rd party device it will have a lot of bugs & glitches you will never find. And it seems you can't underclock it any lower then 350 MHz a core. Anyways I hope this info does you more good then me, since I'm not that good about figuring out specs.

ARM11

 

Differences from ARM9

In terms of instruction set, the ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.

Microarchitecture improvements in ARM11 cores include:

  • SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
  • Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead
  • Unaligned and mixed-endian data access is supported
  • Reduced heat production and lower overheating risk
  • Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
    • Longer: 8 (vs 5) stages
    • Out-of-order completion for some operations (e.g. stores)
    • Dynamic branch prediction/folding (like XScale)
    • Cache misses don't block execution of non-dependent instructions
    • Load/store parallelism
    • ALU parallelism
  • 64-bit data paths

JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.

ARM makes an effort to promote good Verilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. Without such attention, integrating an ARM11 with third party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, the impact of its register-transfer level (RTL) quality is magnified many times.[3] The ARM11 generation focused more on synthesis than previous generations, making such concerns be more of an issue.

[edit]Cores

There are four ARM11 cores:

  • ARM1136[4]
  • ARM1156, introduced Thumb2 instructions
  • ARM1176, introduced security extensions[5]
  • ARM11MPcore, introduced multicore support

 

 

PICA200
 

Specification

  • 65 nm Single Core [7](max. clock frequency 400 MHz)
    • pixel performance: 800 Mpixel/s[7]
      • 1600 Mpixel/s
    • vertex performance: 15.3 Mpolygon/s[7]
      • 160Mtriangle/s
  • Power consumption: 0.5-1.0 mW/MHz[2]
  • Frame Buffer max. 4095×4095 pixels
  • Supported pixel formats: RGBA 4-4-4-4, RGB 5-6-5, RGBA 5-5-5-1, RGBA 8-8-8-8
  • Vertex program (ARB_vertex_program)
  • Render-to-Texture
  • MipMap
  • Bilinear texture filtering
  • Alpha blending
  • Full-scene anti-aliasing (2×2)
  • Polygon offset
  • 8-bit stencil buffer
  • 24-bit depth buffer
  • Single/Double/Triple buffer
  • DMP's MAESTRO-2G technology
    • per pixel lighting
    • procedural texture
    • refraction mapping
    • subdivision primitive
    • shadow
    • gaseous object rendering