drkohler said:
You cannot have active read and write lines at the same clock cycle. It is either you read within the command sequence or it is write within the command sequence. The maximum data rate of the esram is 102G/s, assuming 800Mhz clock and 128bit bus. (It is actually possible for gddr5 to mix reads and writes, since gddr5 has two data clocks but this would be way to complex to explain here). The clocks of the cpu and the apu can be different. Probably creates a mess when sharing data between cpu and gpu, you are on the safe side with fixed 2:1 ratios, apparently. |
So what does reducing the clock speed down from 800Mhz to 750Mhz mean in terms of performance, or is that nothing because the memory clock speed is faster... /me is dumb with these things.








