drkohler said:
Basiclly you then get a PPU in the cell. That PPU is 11.3mm^2. Forget that triple-core with eDram CPU that is only 30mm^2 in size. Not doable unless it is a core much simpler than the ones in the PS3/X360. Again I think the picture of the WiiU board mislabels the eDram (or some other component like the rumoured sound DSP chip or the ARM coprocessor) as "CPU" and the CPU/GPU/(eDram/ARM/Whatever) combo is in the chip carrier labeled "GPU". The images show that all the visible address/data bus lines go to this chip carrier, and not to the small chip. |
You think that Nintendo miss labeled the diagram? I find that unlikely, and 32MB (rumoured amount) of eDRAM at 40nm likely takes up half of the GPU die so I doubt that they would put the main CPU in there as well. Moving I/O and the memory controler would reduce the size of the CPU as well.
Look at the Xenos at 80nm
The smaller die is just 10MB of eDRAM the Wii U suposedly as over 3x as much even at 40nm the physical size would be larger (intergrating it onto the same die will reduce it a bit as well).
If it has unified RAM architecture it makes sense to put the memory controler and I/O etc with the GPU to insure that the GPU gets direct high badwidth access to the RAM and low latency path for video output.
ARM cores and DSP chips are really small, the CPU die is bigger than I would expect for those components and it makes little sense to seperate them out from the other components. In fact as the DSP likely handles thevideo feed for the controler screen, the DSP will be part of the GPU to minimise latency makes sense.
Given that 2 independent sources have implied that the CPU may be slightly lacking it makes sense that the CPU is just a bit small.
Frankly the fact they got performance better than the X360 with such small dies is an extraordinary feat of engineering.
Edit: oppse I forgot that Xenos also has some logic for MSAA with the eDRAM, still point is eDRAM uses a lot of transistors.
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