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lilbroex on 12 September 2012
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zarx said:
lilbroex said:


False, Broadway is a 64bit processor.

  • 90 nanometer process technology
  • Power Architecture core, specially modified for the Wii platform
  • IBM silicon on insulator (SOI) technology
  • Backward compatible with the Gekko processor
  • 729 MHz
  • 32-bit integer unit
  • 64-bit floating-point (or 2 × 32-bit SIMD, often found under the denomination "paired singles")
  • 64 kB L1 cache (32 kB instruction + 32 kB data)
  • 256 kB L2 cache
  • 2.9 GFLOPS

External bus

  • 64-bit
  • 243 MHz
  • 1.944 gigabytes per second bandwidth

Only the integer unit is listed at 32 bit.


IBM says it's 32-Bit

http://raidenii.net/files/datasheets/cpu/ppc_broadway.pdf

I suppose you think that the Pentium 3 is a 128-Bit CPU because it has a SIMD 128-bit Floating point register lol

http://www.ehow.com/list_7446473_pentium-3-specifications.html

 

The instruction set of the Broadway is 32-Bit it's a 32-Bit CPU


Why would I think something that I've stated otherwise many times?


Broadway has a 32-bit address bus and a 64-bit data bus.

You sure we read the same manual?

Three-stage FPU.
– Supports paired single precision floating point arithmetic instruction set extension.
– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations.
– Supports non-IEEE mode for time-critical operations.
– Hardware support for denormalized numbers.
– Two-entry reservation station.
– Thirty-two 64-bit FPRs for single, paired single, or double-precision operands.
— Two-stage LSU.

A 64-bit, split-transaction external data bus with burst transfers.

The store instructions read the 64-bit data from the FPR as a pair of single-precision floating
point data, convert the single-precision floating point numbers into a pair of 8 or 16-bit, signed or
unsigned integer data, and store the results.

The data bus width for bus interface unit (BIU) accesses of the L1 data cache array is 64 bits on the
Broadway and cast out or reload of a 32-byte cache line requires four access cycles. On the Broadway,
this bus has been expanded to 256 bits

The
access interface to the L2 is 64 bits

FPRs User The 32 floating-point registers (FPRs) serve as the data source or destination for floatingpoint
instructions. These 64-bit registers can hold single, paired single or double-precision
floating-point values.

TB User: read
Supervisor:
read/write
The time base register (TB) is a 64-bit register that maintains the time and date variable.
The TB consists of two 32-bit fields—time base upper (TBU) and time base lower (TBL).

 

The memory management module is 32 bit but most components and primarily the data bus(the most important thing) is 64 bit. A 32 bit processor cannot handle 64 bit processes of any form.

 

TLB
Invalidate
Entry
tlbie rB Invalidates both ways in both instruction and data TLB entries at the index
provided by EA[14–19]. It executes regardless of the MSR[DR] and MSR[IR]
settings.To invalidate all entries in both TLBs, the programmer should issue 64
tlbie instructions that each successively increment this field.

You can't issue 64 bity instructions on a 32 bit processor.