I did compare them. What I was saying was that you can't compare them based on number of shaders alone. You have to get into the tyope of shaders, ops per cycle, etc.

Also, yes, I am aware that not all of the shaders may be used at the same time in a non-unified architecture. That's why I said it's efficiency vs brute power and drew parallels between the shaders of the Xenos/RSX and the dedicated/unified RAM of the ps3/360.

Basically, you missed exactly what I was trying to say. I apologize for my miscommunication.

 It seems there is a further miscommunication. I was referring to things related to screen resolution, not texture resolution, and shaders are part of the texture buffer, not the frame buffer. So we both argued on completely wrong pages.

MikeB said: @ LordTheNightKnight Twice the shader power. which every objective test (as in not trying to make Sony, Microsoft, or even Nintendo look better than the other) rates as higher capability No, the Xenos is just more flexible. However the SPUs are also flexible in what ways they can help the overall more powerful RSX. the XDR has a faster clock speed XDR is higher clocked but also offers less latency than DDR2 / DDR3.

I didn't write that the Xenos was more powerful. I wrote that it was more capable. Last I checked, flexibility was a capability. So you countered your own point. Plus I did state that using the SPEs would allow greater graphics, so you tried to counter me with one of the very points I made. This makes me wonder if you even read my post properly.

The XDR comment just shows your ignorance. If it had faster latency than DDR3, then it would have been used as the RAM in the RSX, instead of GDDR3, as the combination of size, clock speed, and latency would make it ideal for VRAM. It doesn't have faster latency, and that's why it's just used for system RAM. It works fine for that, but if you can't get your facts straight, your "IMO" looks more like deliberate lying.

Proofreading! You have that backwards, the pixel shaders handle 5 ops per cycle, the vertex shaders 2 ops per cycle (you did it in the right order when you did the math, though). And stop confusing "per cycle" with "per second". If these chips could only do a few ops per second, we'd be seeing pretty awful graphics. :) I'm not trying to give you a hard time, but these things can be confusing enough even with good proofreading. :)

What's also important is to look at what kind of "ops" you're talking about when you say 5 pixel shader ops per cycle on the RSX vs. 2 on Xenos. As I understand from the spec sheets (which may or may not be detailed enough for this kind of analysis), the RSX can do two vector ops per cycle and two scalar ops per cycle, plus fog, whereas Xenos does one vector and one scalar op per cycle. Well, the fog step happens at the very end of the shader -- the output fragment gets blended with the fog color. This doesn't happen every cycle, it just happens "free" at the end of the process. The same thing happens on Xenos, they just don't count it as a 'shader op' on the spec sheet, since it really isn't one. So what I see is 48 pipelines * (1 vector + 1 scalar) vs. 24 pipelines * (2 vector + 2 scalar) + 8 pipelines * (1 vector + 1 scalar). Which gives:

RSX: 56 vector + 56 scalar shader ops per cycle @ 550 MHz
Xenos: 48 vector + 48 scalar shader ops per cycle @ 500 MHz

I can see stating that the RSX is the more powerful chip, but let's not overstate it.

You got me with the proofreading, lol. When I wrote "per second" I was contemplating adding some calculations dealing with the 500 and 550 mhz clock speeds. I decided against it, and threw in the line, "The fact that the RSX is clocked at 550mhz compared to just 500 for the Xenos also gives it an advantage." I guess I just still had the word "second" on the brain.

Also, I was not aware of nVidia counting fog as it's own operation. If this is true, then yes, the GPUs are far closer than I thought.