kars on 11 March 2007
Kwaad said:
The C2D changed things for the better. But still once agian, it is not the way the cell works.
The cell has 64mb memory on each SPE. (dedicated) meaning that one SPE can access that memory at 100% speed. or all 8 SPEs can access their memory at 100%.)
Where did you get your numbers from? 64 mb per SPE on a single chip. Did you ever take a look at the size of the on-chip cache, compared to the rest of the processor?
Every SPE has a memory of 512 KB (iy your numbers would be true the cell would have more memory in its SPEs, than the amount of memory, that can be used by the cell on the PS-3 (256 MB). In fact a major weakness of the cell is its lack of a unified cache that would allow a faster and easier interaction of the single units, especially in siturations where you do not have evenly distributed code with a weak interaction. If they have to access the local memory of another SPE, you will have to send a message through the internal ring bus, while multicores with a unified cache can access these informations directly. But such a cache needs space (and transistors).
A cell has advantages if it is sufficient to load its memory one time and then only exchange data. If you have to switch the programs multiple times you have to load the program through the common bus. The same situation on a system with the unified cache can mean that the new program is already in the unified cache and you don't need to load it from the memory. If an SPE is used by one program it is locked by this program, even if it is waiting for data. On a multi-core this process does not use its share of processor time and other processes can be run in the mean time. So the situation is not as simple as you think. The cell was primarily developped for cluster applications. You have one program that runs on every SPE all the time. It only uses its local memory add one general multi-purpose-core for caching, control and secondary programs. Which capacities will I no longer need on the chip , and how many parallel SPEs can I put on this chip.
This was the basic idea behind the cell. It's weaknesses were well known, because its limitations are exactly the capacities that were not necessary under this circumstances. It was not so far fetched to add to it a kind of pipeline handlling for multi purpose situations, but it was never designed as a kind of main processor in a game console.
I moved it.
