haxxiy on 23 September 2024
| haxxiy said: The maximum data bus width for soldered LPDDR5 is 32-bit, so at 7500 MT/s = 30 GB/s per module. If I were to hazard a guess it'll be either three 32 Gb modules at 32-bit or six 16 Gb modules at 16-bit, so that's more like 90 GB/s. |
I just wanted to issue a small correction: I realized the prototype board has two modules of RAM only, so if that's the same for the final hardware then it's featuring two 48 Gb modules, a configuration I didn't know existed before, and definitely (being soldered RAM) 60 GB/s of bandwidth total.
