| Chrkeller said: Maybe Perma can weigh in with his expertise. I would assume if frequency is reduced by default bandwidth is as well. I don't think one can be reduced and not the other. I mean the frequency is basically instructions.... fidelity can't be faster than the instructions. Maybe I'm thinking of it wrong. |
Bandwidth has a direct relationship to frequency and bus width.
You reduce memory frequency by 20%, you reduce bandwidth by 20%.
Frequency isn't instructions, frequency is what part of the electro-radiation spectrum it occupies. - The higher the frequency, the more the signal attenuates and degrades, but the higher the potential information throughput.
That's the dumbed down version of it anyway.
Ram frequency has been a bit stupid for years anyway.
When we went from EDO Ram to SD Ram we kept it as a "standard clock rate". - When we moved to DDR/DDR2/DDR3/DDR4/DDR5 we moved to transferring data on the rising and falling edges of the clock-cycle and so memory manufacturers with all their advertising-prowess started to inflate clock-speed numbers, I.E. DDR400 when it was actually running at 200Mhz internally.
| padib said: So the bandwidth, as far as I understand it, is directly related to the circuitry of the motherboard. The busses and the actual wires on the chips themselves define the bandwidth. This can't be changed after the parts are manufactured. |
No.
HBM for example completely side-steps the motherboards limitations by leveraging an interposer.
The bus is determined by the memory chips individual interface size determined in bits and how many chips you have.
So you can have 8x 16bit memory chips operating at 1ghz and it would provide the *exact* same bandwidth as 4x 32bit memory chips operating at 1ghz.
Or you could have 16x 16bit chips operating at 500Mhz for the exact same result.
It's extremely flexible because memory transaction can be made extremely parallel. - Obviously on the other-side of the memory equation you need a memory controller that can handle all of that... And higher clocked Ram or wider memory buses tend to require a more complex memory controller to manage it all.
In short you can have DDR2 Ram be faster than GDDR6 Ram, it's completely dependent on how many memory chips you want in the end.
| padib said: The clock speed is defined by the electrical pulses and can be regulated at the electrical level, clocked higher or lower depending on what power is pumped into the processor. This one can change. |
Not exactly.
Clock speed is determined by the electrical characteristics of the silicon itself, it's got a firm relationship with voltage and transistor type and size... Governed by Dennards Scaling Law and Moores Law as well as a variety of other factors like the patterning, defect rates, geometry of chip features and more.
Some chips have higher leakage than other chips as the main processing pipelines may lack appropriate levels of dark-silicon insulation which holds back frequency... And it doesn't matter how much power you pump into it, you won't get any faster.
| padib said: Think of the bandwidth as the number of lanes on a highway, and the clock speed like the speed of the cars. |
This is a false picture to paint.
The number of highway lanes would be the memory bus width defined in "bits". I.E. 64-bit wide or 128-bit wide is common for mobile devices these days.
Clockspeed is how fast the cars are traveling on said road.
And bandwidth is how many cars are on said road.
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