By using this site, you agree to our Privacy Policy and our Terms of Use. Close
haxxiy on 10 May 2024
Edit Thread
Pemalite said:

This has been an issue for years... The smaller we make the chips, the higher the chances of leakage... The more leakage, the more heat, the more limited we are with clockrates.
...So chip designers started using dark silicon around parts of the chip as a way to insulate against that which we saw with Pascal... It does make the chip larger.
nVidia also deployed a few extra tweaks like decoupling parts of the chip to drive up clockrates as well.

Obviously companies like TSMC and Samsung took note of that and started making specific tools for various process nodes to capitalize and optimize for it as well, hence why there are a dozen different types of "7nm".

..Now when we actually get to 3nm, not the advertising 3nm... But geometrically real 3nm... The real issue will end up being Quantum Tunneling. - But we are not there yet and won't be for years.
I.E. TSMC's "3nm" process is using a gate pitch of 48nm with N3E being 24nm.

That's true, although I was thinking specifically of increases in parasitic capacitance and leakage with sub-10 nm contacts. Apparently, these can be significant enough to decrease frequencies at a constant power density depending on the node.

The 5 nm threshold for mobility collapse from quantum tunneling comes from the width of the silicon transistor fin, which is around 8 nm for TSMC's N3, not gate or metal pitches. In fact, the limit is more like 7 nm for FINFETs, so TSMC is skirting the line with N3... and everyone else has moved to GAAFETs.

Nodes used to be named after half of the minimum metal pitch (so that'd be 24/2 = 12 nm for TSMC's N3) but logic gates have been scaling better than DRAM and now are the smallest feature. So the naming scheme isn't that outrageous, TBF.