| haxxiy said: Mind that especially beyond 3 nm the logic of increasing clocks with smaller nodes is expected to reverse, so I foresee more companies pivoting to an 'efficiency' pitch as a way to explain why they're going for broader, slower designs instead of pushing the envelope as before. Two birds with one stone, so to speak. |
This has been an issue for years... The smaller we make the chips, the higher the chances of leakage... The more leakage, the more heat, the more limited we are with clockrates.
...So chip designers started using dark silicon around parts of the chip as a way to insulate against that which we saw with Pascal... It does make the chip larger.
nVidia also deployed a few extra tweaks like decoupling parts of the chip to drive up clockrates as well.
Obviously companies like TSMC and Samsung took note of that and started making specific tools for various process nodes to capitalize and optimize for it as well, hence why there are a dozen different types of "7nm".
..Now when we actually get to 3nm, not the advertising 3nm... But geometrically real 3nm... The real issue will end up being Quantum Tunneling. - But we are not there yet and won't be for years.
I.E. TSMC's "3nm" process is using a gate pitch of 48nm with N3E being 24nm.
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