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[Pemalite]

numberwang said: Pemalite said: The 6650XT is not just an overclocked 6600, it's an overclocked 6600XT. - Different chips. The 6600 actually has less CU's, 56GB/s less banwidth... But also a 50w lower TDP than the 6600XT. The 7600 is actually a great replacement/upgrade over the vanilla 6600, but we also need to compare them based on price... Where the 6650XT is actually cheaper than the 7600, making the 7600 a bad buy. And if we compare it against the 6600, the 6600 is $100 AUD (25%) cheaper, so if you are on a really tight budget, might be the better choice anyway. The video is addressing the naming issues. The 7600 has the same number of CUs as the 6600XT (4 more than the 6600) so 7600 vs. 6600XT is the direct comparison for RDNA3 vs 2 architecture.

I get that, but it's not the 6600XT replacement, it's the 6600 replacement.

It still needs to be compared against the 6600, 6600XT, 6650XT... And I would even include the 6700XT at this point due to it's attractive price point.

JEMC said:

Darc Requiem said:

It will be a lower degree of difficulty for AMD. Their C cores are the same architecture. The main difference is the reduced cache. Intel's are different architecture entirely from their P cores and lack hyper threading.

But, wouldn't the shared architecture make it more complicated? If both types of cores are virtually the same except for the cache, and maybe the clock speeds, how will the OS decide which cores run what?

Using the core frequency doesn't seem to be a valid option or Intel would have gone that way.

This is the issue.. And mostly due to a lack of information causing many unknowns.

Whenever you have cores of mixed capabilities, either the processor or the operating system has to be cognizant of what goes where to get the best results, that means you need additional information/analysis of what is happening in every thread.
...And that is why we got Windows 11 as it enables this capability at the software level.

Intel's approach was then to introduce the hardware-based Thread Director which works with Windows, it achieved this by having the thread director analayze every thread, detecting the amount of loads, stores, branches, average memory access times, patterns, and types of instructions... And communicate that back to Windows in order to determine which core it needs to be scheduled on.

AMD didn't bother with this with the Ryzen 3D cache chips, so while it did issue patches that allowed Windows to determine which were the cache-heavy cores, there was no hardware based solution on the CPU itself to communicate with the OS...

Part of the issue was, some threads were cache heavy, some were more clockspeed sensitive, Windows doesn't perform any intrinsic analysis to determine which thread would be best on the cache or higher boost clock cores, so it assumed the higher cache cores were the best for everything.

So hopefully AMD takes a hardware approach, it will require an extra chiplet or perhaps a change to the I/O die (Or both), but it's simply going to provide better results.