| haxxiy said: I get what you're saying but Turing, Ampere, RDNA3 were all neutral or underperformed node gains. The last time a new architecture had a meaningful jump in efficiency with other factors being equal was with Maxwell and RDNA1. That would mean simply refined architectures have been faring just as well in efficiency, on average, so I'm not sure there's a trend here. That being said, at least for the next generation, there's room between TDP and non-RT gaming in the 4090, as well as the possibitlity of making a bigger chip with safer clocks even with meager efficiency gains in 3nm... |
The issue is, nodes aren't decreasing in geometric feature sizes like they used to.
The fabrication "node" size is just an advertising number and not a representation of node improvements or actual geometric size, it's why Intel moved to a different naming scheme.
TSMC/Global Foundries/Samsung have also been guilty of decreasing just the BEOL or FEOL and calling it a "new" node... When historically new node jumps include a shrink of everything, rather than just one aspect.
It does mean that we tend to see more of a linear improvement in chip manufacturing over time rather than big jumps.
| Captain_Yuri said: A: Imo at best the uplift of increasing memory bandwidth will be a few % because of how power limited the APU is. We see this because increasing the power netted big gains even though it's at the same memory speed. So even if we are generous and say 15% gen on gen uplift at 25 watts, I think it's pretty disappointing. Perhaps RDNA 4 will fix a lot of RDNA 3s short comings as Lovelace certainly fixed a lot of Amperes shortcomings after Nvidia went dual fp32 for the first time. |
This. I have been playing with AMD notebooks for years... And TDP has always been your biggest limiter to performance.
If you know a game is lightly threaded, you can actually increase CPU performance by setting the affinity to enough cores (Ideally spread all over the chip rather than in one section) and get higher boost frequencies.
Sometimes, playing with power management and limiting the clockspeed of the CPU, allows the chip to funnel more TDP into the GPU if you know your TDP bound on the GPU side. - This was a tactic I used on my old Ryzen 2700u notebook with Vega 10 graphics... I still got improvements with this method on the 4700u, but it was lessened due to efficiency improvements. - The 2400mhz vs 3200mhz bandwidth between devices wasn't a deal breaker unless I started to push the higher 1080P resolutions, which was when the fillrate limits kicked in.
RDNA 4 needs to take the best parts of RDNA 3 (Which is actually not a bad architecture, just needs more refinement) and dial home that RT.
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