Pemalite on 14 March 2021
Bofferbrauer2 said:
I had a similar idea, just increase the size of the L2/L3 caches and Rocket Lake would probably have been beaten with less. |
Indeed, that is another approach, but still would require some investment in optimizing the chips layout.
eDRAM could have been off-chip but same package and built at a less congested 22nm node, so 14nm chip supplies wouldn't be impacted.
The eDRAM essentially functions as an L4 cache when the iGPU isn't using it.
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