LurkerJ said:
For a comprehensive and a visual explanation of decoders and out-of-order execution, watch this video (explanation of decoders starts around the 6th minute). |
Answering @Jumpin I partially gave a possible way for AMD and Intel to get out of the corner, but there's more, I'll add it below.
Alby_da_Wolf said:
Both AMD and Intel could decide to give direct access to their microarchitectures, bypassing the x86 translation layer that would be used just for legacy applications (and could be gradually abandoned when emulation starts reaching the native performances of the last x86 CPUs, but could be dropped altogether, saving silicon, for CPU models targeted to users not needing legacy). |
Apple-like solution is perfect for big device makers needing just one or two SoCs at a time for their mainstream platforms, like console makers, or for HUGE device makers needing a higher, but still quite limited number of SoCs, like Apple.
So a 10th gen RISC SoC with a bypassable x86 to RISC translation layer using a subset of the available cores to deliver 9th gen BC could be feasible, the old gen performance capable translation layer would add little more silicon to a 7 years newer highly parallel RISC SoC.
But the SoC solution, as the video you linked correctly pointed out, isn't suitable to the whole PC market, that provides a really wide range of single components and an incredibly huge number of possible system configs that would be a bloodbath to serve with an excessively wide range of SoC's, not to mention that a single PC config, even using APUs, so fixed combinations of CPUs and GPUs, still offers the possibility of expanding RAM, always on desktops and very often on laptops, except the ultrathin ones with RAM external to CPU or APU, but soldered on the MoBo.
For the PC market I can still see the Apple-like RISC SoC solution doing wonders, but it will still need at least one more feature, a very high-speed (higher than current Northbridge AMD and Intel ones) external bus to connect the SoC to external RAM sockets, possibly treating such external RAM as L5 memory, while internal RAM and caches would be Levels 1 to 4. This would add costs, but lower than making enough SoCs for all the different needs of PC users.
A very high-end solution, viable only if the OS supports it, so good luck to users of non server versions of Windows, would be that the user needing more RAM adds one or more whole SoCs, this is surely unthinkable even for average mid-high end users, that could need to add just RAM for some memory intensive tasks to the fastest SoC they could afford. And all this not even considering users needing not only larger RAM, but also faster GPUs than those included in the SoCs, here there is an even higher obstacle, new high-end GPUs are released more often than high-end CPUs, making the highest-end SoCs quickly outdated in their GPU side.
So the classic PC system model is here to stay for some time, but console makers, that already order and help design customised chips for their systems, really haven't insurmountable obstacles to switch to Apple-like SoCs for 10th gen, and adding 9th gen HW BC won't be too hard either.