vivster said:
I'm not a chip designer so for me the biggest question is why do it like that and not "just" introduce a 3rd datapath to be able to use all cores simultaneously. It would undoubtedly make the chip more complex and engines and interconnects would need to be adjusted, but is that the big issue? Is there a mechanical issue to it? Is it a cost saving measure? Are whatever controllers not able to handle more than 2 paths? Considering they are huge chips they probably did not have the real estate to just double both kinds of cores, so they just increased the important ones. |
Space and power consumption constraints, basically what you propose is what will happen eventually, it's just that Ampere is already large and power hungry even on Samsungs 8nm node, so they had to make some compromises.
Core flexibility does cost transistors... And because fabrication improvements are slowing down, sometimes going with simpler core/pipeline designs and optimizing for projected workloads is your best approach to getting the best possible performance... And nVidia is changing focus towards compute as that is what future projected workloads demand. (I.E. Ray Tracing is an inherently compute constrained application currently and Tesla is seeing massive growth.)
AMD also recognized this years ago, hence why Graphics Core Next became a thing... Sadly Rasterization was still an important workload hence why they decided to branch out GPU designs, CDNA for Compute, RDNA for Rasterization.
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