"How is it more power efficient? And how would it effect latency? And how does any of that even matter?"
You know that exsample with discribeing the a wormhole, as a piece of paper you fold, and you punch through it? to shorten the distance?
Its like that.
The futher apart these things are spaced out, the higher the power draw (and travel time).
By makeing usage of the 3rd dimension, you can have a chip ontop of a chip, with a bridge (thats a very short distance) between the two.
This means that parts of the chip, that would sometimes be spaced out far apart in a 2D flat chip, and thus have to move longer distances, can now, have parts that dont need to do that, because the stacked chip ontop is bridged to the one underneath/ontop of it.
You sound like you dont understand the differnce from stacking something ontop of one another, with no comuncation between chips, vs a chip designed around a 3D plane.
Theres massive gains for doing so.
From neogaf: mckmas8808
"Compared to this traditional 2D architecture, 3D ICs provide several significant advantages:
1. Footprint
Obviously, stacking multiple dies atop one another produces a chip that takes up less space than if those dies were side by side. If the layers are aggressively thinned, a multi-layer 3D-IC is actually no thicker than a traditional 2D chip. The tiny size of 3D-ICs is extremely valuable in miniaturized devices such as cell phones and IoT applications.
2. Speed
Dies stacked in a 3D chip are much closer together than chips on a circuit board. The shorter distances allow electronic signals to travel more quickly from one component to another. 3D stacked devices have shown as much as 5x speed improvement over comparable 2D solutions.
3. Power
Shorter connections automatically require less power, but 3D ICs have another power-saving trick. When an electronic signal travels from one chip to another, it passes through special circuitry that screens out any accidental electrostatic discharge (ESD). These ESD filters consume energy. Signals that travel from one layer to another within a 3D-IC do not require ESD checks. Tests have seen as much as 90% reduction in power consumption.
4. Heterogeneous Integration
Because the layers in a 3D IC are manufactured separately, they can be built differently. This is more important than it might seem! The process in which a die is built affects the behavior of the components on that die: one process makes better capacitors, another makes faster transistors, etc. Even more interesting, the layers may be built at different process nodes – that is, the electronic components may differ in size. This affects the cost, complexity, and performance of each layer. It is even possible to stack layers that are built of different materials. All of these possibilities mean that a 3D IC can combine the best of each process, node, and substrate without compromising some components to accommodate others. In fact, a multi-die stack can contain combinations that are flatly impossible to achieve on a 2D chip."
"How is it more power efficient? And how would it effect latency?"
Does it make sense now?
its like even if you have a gas-effecient car, the longer the road you travel, the more gas you'll use.
3D stacking = shorter roads.
Also long road vs short road = less time travelled.
"how does any of that even matter?"
Because consoles are limited in scope by power consumption?
The more power something uses the bigger the cooling unit, the more bigger the fans or the more noisy (usually).
This allows for more performance in a smaller size, less cooling issues/noise.
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Now onto the Variable clockrates thingy you asked about.
What is overhead?
We'll if you "lock" a clock rate, you actually dont lock the power consumption of a thing.
Because depending on workloads, even af same clock speeds, differnt tasks will require differnt amounts of power consumption.
So... how do you fix that? If you want to lock in a clock speed, and you know your power consumption is going to jump up and down, even at same clocks?
Well the "fix" (so its not unstable or crashing) is to design it around always haveing access to more power than it normally needs.
So its always just "wasteing" power, to make sure, it can run stable, at a locked in clock rate.
If you design around a locked power consumption, this issue is avoided.
Instead you will have your clock speeds go up and down, based on workloads, to stay within a given power consumpion.
This means you dont have to "waste" a certain amount of power consumption, when not needed.
This means you can design a chip thats more power effecient, and thus also easier to cool.
Also because its load is always locked, you can design the cooler around it, so it wont ramp up and down and be crazy noisy on some games.
What are the downsides to this? Like cerny said, sometimes it ll power down like 2% or so in cpu/gpu performance, but saveing upto 10% powerconsumption.
Developers are going to have to accept that they cant always use 100% of both cpu+gpu at the same time, they might have to take 2% from one or the other, if it reaches the power consumption cap.
What are the upsides to this?
Well you can maximise performance to a higher level, because you get around the "bouncy" powerconsumption levels like this.
Another could be, you could use it to have a more effecient chip. (higher performance/watt, because no wasted overhead).
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About the SSD and bottlenecks.
Do you know for a fact that the Xbox series X has dedicated hardware units, to offload the cpu/gpu(cashe), and do everything Sony mentioned, when it talked about SSD and bottlenecks?
Suppose Xbox needs to do some of these funktions, but instead of offloading it another unit, runs it on the CPU?
That could mean the extra mhz the Xbox series X has, is used on that, and the playing field, in CPU terms are closer than speeds might suggest?
or some of these tricks used by sony, even if not taxing for the cpu, might just be done at slower speeds, compaired to sony's solution.
(because they might lack such units)
Why did sony get rid of the "overhead" (waste of power) & use 3D stacked chips (energy effecient) ?
I think its to drastically reduce the size of the chip.
The difference was already quite large (36 cu vs 52 cu), the power effeciency was used to run the chips at higher clock rates.
This is why the PS5 chip runs at such high speeds for its GPU. Its the gains of smart techniques (turned into savings on the chip costs).
This allows for a smaller and probably much cheaper chip.
