Pemalite said:
fordy said:
That's because the more advanced compilers tend to exploit a lot of the CPUs hidden features that a lot of programmers never take into account, such as interleaving instructions for optimised use of SMT, re-ordering assembly language for better use of eg. Intel's branch prediction logic, down to storage order and spatial locality.
From what I can understand, the Cell used the PowerPC instruction set. However, the way it processed these instructions was different to IBMs other CPUs, due to the architecture of the Cell. Therefore, it would make sense why ND might have manually optimised some code using assembly language, especially if the PowerPC compilers used were optimised more toward the IBMs CPUs and not the Cell.
However, on an architecture as old and thoroughly optimised as x86/x64, the benefits of assembly language over a well advanced compiler range from absolute minimal to counterproductive.
That being said, there may be a little gain if compilers aren't yet optimised toward Zen2. However, I doubt this will be anything like we saw with the Cell.
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It's a bit of a stretch either way as it was an uncommon practice on the Playstation 3 even for a tiny part of a games code base.
As for compilers on x86... From what I remember a few years back, x86 compilers tend to have an advantage on Intel processors as Intel worked with developers on making the compilers shine on their hardware, plus they had the majority of the market locked up... So AMD specific instructions tended to fall by the wayside. (I.E. 3D now!)
That is rapidly changing now of course, Zen/Zen+ has been on the market for a few years and Zen2 is quickly ramping up, AMD's market share is also growing rather significantly... So that is likely to have a flow on effect.
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Though I wasn't talking about feature sets like MMX or 3DNow. Even if Intel and AMD both make x86/x64 processors, the way they meet the instruction set requirements can be achieved using vastly different methods. Some use direct hardware, and the level of complexity determines how many clock cycles a result can be returned. Intel themselves have been using Microcode from a RISC based internal module since the days of the P6. It's those differences where compilers optimised for certain manufacturer hardware comes into account; It's still instruction code compliant with all compatible hardware, but performs better with specific hardware.
As an example, Intel optimised x86 code can utilise answers from branch instructions quicker, thanks to their stupidly complex, yet surprisingly accurate branch predictor logic. Likewise, AMD has logic where code executed in a certain order can achieve a result quicker than Intel hardware. Methods like prefetching and ILP have also made a huge difference in optimisation considerations.
The same goes for IBM PowerPCs and Cell; both use the PowerPC instruction set, but achieved those outputs from different hardware methods.
Compilers optimised for certain hardware are hardly new. I started x86 programming in 1995, and I remember them being around then; Usually Intel, AMD and Cyrix.
