Unfortunately the information is pretty scarce at the moment, but according to WCCF the 64 CU limit is gone and according to a leak by KOMACHI there are 8 SEs in Navi 10, which would be very good news if true. That would mean we will see performance improvements in the geometry/rasterizer/zROP bound workloads, which becomes more prominent when scaling beyond 40 CUs (10CU/SE). Most likely the 64 ROP limit has been increased as well even though the midrange cards to be introduced in July probably won't feature more than 64 ROPs.
It will be interesting to see where the 25% IPC comes from and under what conditions they have measured it. Some will come from the improved cache and most likely widened data paths into the CUs as well as some new instructions, but it's unlikley that would yield a 25% IPC. Introducing separate integer units in the CUs similar to Turing could be one explanation but I'm sure AMD would have touted that if that was the case, so the IPC increase probably comes from several minor improvments.
All in all, at least some notable improvements from AMD, even though they still lag nVidia by quite a bit, and good news for the PS5, in particular the performance/watt improvements. Still no confirmation that Navi supports VRS, which when utilized properly can give a significant performance boost (I'm pretty sure PS5 will support it though, but that's pure speculation on my behalf). Hopefully AMD will be more informative at E3. 
