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Straffaren666 on 15 March 2019
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Pemalite said: 

AMD will be required to sacrifice some of the "density" in order to reduce leakage and noise so they can dial up clock rates.

Yes, and a 3x density improvement should accommodate that.

Pemalite said:

Navi is Graphics Core Next based... Graphics Core Next isn't really designed for any particular node, it started life out at 28nm remember, got shrunk to 14nm and then 7nm... All the while iterative updates were introduced into the core design to extract more performance.

Navi isn't a new design built from the ground up. That's the ultimate crux of the issue, it's just more Graphics Core Next, nothing special.

At the end of the day, regardless of GPU, AMD's designs are inefficient, old and outdated... And sadly that is going to reflect on the capabilities of the next-gen consoles.  

There's a big difference between designing Navi for being built on the 7nm process node and shrinking Vega 7 to 7nm. Designing a SOC on the 7nm node is very expensive. Vega 7 is a low volume niche product and the shrink to 7nm was most likely a bare minimum effort.

Pemalite said:

Graphics Core Next already has a multitude of bottlenecks inherent in it's design, it's why it's a compute monster, but falters in gaming.
Blowing out functional units will simply compound those inherent issues.

In saying that, Graphics Core Next is also highly modular, AMD can pick and choose what parts of the chip to update and leave the rest identical, which reduces R&D and time to market.

But the main reason for why Graphics Core Next won't scale beyond 64 CU's is simple. 
Load balancing. - Which also occurs on the front end as well... And because the Geometry and Raster Engines are tightly integrated in a multi shader-engine outlay design like Graphics Core Next... The screenspace is split between the 4 engines and their respective clusters evenly.

Imagine you are splitting your display into 4x parts, the load balancing needs to be dynamic, so those parts shift so that the load is equal across all 4x shader engines.

What happens if we add more Shader Engines? It reduces the utilization across all the CU's. - There is only so much Screenspace that you can dynamically allocate with usable work to keep the entire chip busy. - One of Graphics Core Next's largest issues is effective utilization... Which was a much larger issue with the prior Terascale designs, hence why AMD introduced VLIW4 to increase utilization.

I don't believe there is a need for making a departure from GCN for AMD. All the current bottlenecks are not any major flaws in the architecture and can be overcome by evolutionary updates of the various units.

Load balancing is not a major issue yet. The number of pixels per CU for 16 CUs@1080p is the same as 64 CUs@4K. There are not any significant inefficiencies when crossing the 16CU boundary at 1080p and the same applies when crossing 64CUs at 4K.

Last edited by Straffaren666 - on 15 March 2019