shikamaru317 said:
I believe he was referring to Moore's Law, 7nm was once believed to be the smallest that transistors could ever shrink to based on Moore's Law, because anything smaller would cause quantum tunneling which allows power to escape through the walls of the transistor. However, a new manufacturing process called Gate-All-Around was discovered which will allow that limit to be circumvented at least for a few more die shrinks. So 5nm and smaller manufacturing process will be using Gate-All-Around FET rather than finFET. I do believe that 1nm is the lower limit even with gate-all-around though, so in order to circumvent that lower limit it is currently believed that we will have to design an alternative to binary computers, such as quantum computers, which are still in their infancy. They'd better get their move on making quantum computers work, because that 1nm limit will be reached by the late 2020's most likely and chipsets basically won't be able to get any more powerful after that without making them bigger, more power hungry, and more expensive. |
The use of multigate devices to come close to physical limits was a thing expected all along. None of these manufacturing nodes are what the ITRS used to consider 7 nm or 5 nm, though. TSMC's 3.5 nm (and presumably Samsung's equivalent 4 - 2 nm GAAFET nodes) are what it should have been called the 7 nm node, if foundries hadn't transformed technical node names into marketing names. That's why Intel's 10 nm (which is actually a 11 nm node according to ITRS's standards) is more complex and efficient (though slightly bigger) than Samsung and TSMC's 7 nm nodes.
The next step for more demanding applications, mid to long term will likely be 3D circuitry (bonus points if CNT or copper-CNT connections are viable) but price and heat might pose a problem to apply it in future generations of consoles.
