| Areaz32 said: Also isn't 7nm a theoretical low point due to quantum tunneling? |
There are ways to mitigate and get around the issue. There have been 3nm test chips and 2nm transistors and 1nm gates.
But I think we will end up following the trend that NAND has done.
We were shrinking NAND constantly... Which was fantastic.
We were making chips smaller and cheaper, but at the cost of endurance... (Processors have a similar endurance issue thanks to thermally-assisted tunneling/electromigration, CPU's these days simply won't last as long as older chips.)
So, NAND went the opposite direction, they made chips larger on an older, cheaper process, but then they stacked more chips on top of each other.
You still have high quality SLC and MLC chips on newer process nodes though for markets that demand it.
AMD with Thread Ripper decided to use a "Mesh" to stitch multiple chips together as it was more cost effective than one giant chip as you could then get more working chips out of a single wafer.
Lots of ways to get reduce costs and increase performance even at our current technology level, chip designers and fabs are starting to think outside of the box. :)
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