AMD’s Vega 10 High-Bandwidth Cache Controller aims to improve performance by almost 100% in minimum FPS

[Alby_da_Wolf]

Pemalite said:

God dammit. Why can't the explain how they achieved what they did with this cache? I want details, not claims.
What kind of  cache is it? Is it using existing DRAM on the GPU? A proper high-speed cache on the GPU itself? Is it powered by combustible kittens from outer space?

***

It's use however is going to be extremely limited.

Low-End GPU's already have more memory than they could ever possibly hope to use...
The mid-range could see some benefit, especially when manufacturers sell a version of a GPU with less memory to save on costs. (Like the Radeon RX 480.)

The High-End typically always has enough memory to make such a feature worthless anyway, with a few-edge case exceptions like Fury and Fury X, but that was because it was using such a new memory technology. (HBM/Stacked memory connected via an Interposer.)

If this "cache" takes up transistors and thus drives up costs and it's benefit is only in low-memory situations, then I would rather they didn't bother and just threw more GCN pipelines in.

Probably if they bothered doing it, they're considering to make a base model Vega aimed to those that want more than Polaris, but not the true highest end, and probably they'll use it in high-end Ryzen-Vega APUs too.
About its cost in resources and money, MMUs used to be separated chips before the 486 and the 68040, then they became small enough compared to other units like ALUs and FPUs to be included with them in a single chip, and with time their share of the total chip size became smaller and smaller, particularly in the high-end CPUs with L1 and large L2 on-chip caches and high-end GPUs with many computing units.