Intrinsic on 15 January 2015
| captain carot said: Yes it does. Normally gates get halved as well. You can as well get the packing density up within one fabrication step. Actually AMD is doing that right now. RV670's die had 660 Million transistors at 55nm on 192mm². Bonaire has 2.04 billion transistors at 28nm on 160mm². Partially that is due to other structure, Bonaire having cache etc., so a better comparison woild likely be Pitcairn, 4 times the shader units, etc., cache with slightly more die space. 2.8 billion transistors on 212mm². Now take a look on Carrizo. AMD says Carrizo will be packed much denser so it will have 30% more transistors on the same die space at the same process. And yes, manufacturing processes are behind, but 20nm is up and running, it's just that at least most of it is reserved for mobile SoC's and Nvidia said they'll likely skip it. 14nm is in early production phase on some fabs. Samsung is at it right now, AMD is right on track according to themselves. |
Noted, and you're completely right. will edit my main post. Thanks, must have got my math all mixed up.
