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megafenix said:
fatslob-:O said:
Well god be damned! I made alot of people really mad here while exposing frauds all at the same time LMAO.


talk about fruads like edram for just cache when shinen already said is more than that

want me to prove it

even by today standards, gpus pack only kilobytes for caching, not megabytes

do you want a proof on this?

 

answer quicly, or i will be forced to show everyone here proof of your bullshit and a backup for shinen as well diredctly from ati

 

will you apologize or continue barking?

decide already, i have wasted many posts asking you this and you just continue avoiding it

 

very well, i will have to lift my hand it seems

you have 5 minutes

apologize and recognize your mistake about caching, or make my checkmate move to expose you even more

seems you  like to be beaten up one time and another

 

well, time is up, sorry dude, you did this to yourself

 

 

i forgot, you actually dont like to investigate, dont worry, here

 

so, are 32 megabytes really that tiny compared to the internal caches of the gpus for tmus and simd cores?

32 megabytes vs 8KB,16KB or 64Kb?

 

who wins?

if the l1 cache, texture caches and the global data share are only some kilobytes for caching, shouldnt the 32 megabytes of edra be considered assomething like ram for the gpu?

dont forget that there ar additional 3 megabytes of faster edram+sram, so in reality we are talking about 35 megabytes of embedded memory

 

and this is howthe great expert in pc tech stuff falls

or maygbe this is how a big troll falls

@Bold Damn your understanding of cache is extremely limited LOL. Must suck not to know anything on this subject. 

http://www.merriam-webster.com/dictionary/cache

This post tells me you have a severe lack of understanding memory hierarchies. The reason why 32MB of eDRAM is considered cache and not main memory has to do with the fact that it has a lower access time than the main memory as evidenced to it being integrated on GPU. The intel iris pro 5200 treats it's own 128MB eDRAM as an L4 cache because it's not a part of the main memory. It is instead used to buffer extra pieces of data that the L3 cache requested. 

Your the one that supposed to owe me an apology for your atrocious behaviour.