Adinnieken said:
The GPU is capable of accessing both the eSRAM for read and write purposes. It has four channels to that memory. In addition, in parrallel it can also read from or write to the DDR3 memory, and it has four channels to that memory as well. |
That is not how memory controllers work. I have explained (to the best of my insight into the technology) how the gpu mmu crossbar works in another thread. I'm not going to do that again.
The 204GB/s number thrown around by ms is completely bogus (and probably corresponds to creative accounting for some rmw cycles inside the gpu caches). At this time, I stick with a maximum achievable bandwidth of approx. 150 GB/s (for some peculair access patterns). Until a REAL ms engineer comes forth and explains the REAL functions of the gpu crossbar, we should take the numbers forwarded by ms pr speak as rumours (or extremely creative accounting).
