drkohler said:
There are more questions than answers on this slide. Just a few of them: 1. Does the cpu access the ddr3 with 30GB/s max? What with the rest of the 68GB/s? 2. The memory transfer between gpu and esram is a mystery. You CANNOT transfer 109GB/s in both directions the same time with only 4 memory controllers. 3. Where are the two dma controllers of the gpu? Are they in reality the two "swizzle copy" dme engines? 4. Where are the 4 dme engines located (if two of them are not the gpu dma controllers), and to what do they connect at what possible speeds? 5. What is that thin black line between cpu and esram busses? (we now know the cpu can't access esram directly) 6. What is the speed of the bus between gpu mmu and cpu mmu? Who drives the bus?
There are other finer details that are unclear in that slide |
1. Yes the cpu does access the whole DDR3 at 30GB/s max and I believe that 68GB/s was meant for the GPU to the DDR3.
2. Ehh I wouldn`t worry too much about the bandwidth speeds considering that eSRAM is only used too save bandwidth from the GPU having to access the precious 68GB/s.
3. You are right about it missing the DMA on the diagram but I'm willing to bet that it would have to there on the GPU otherwise it wouldn't be able to access the system memory and we all how dumb it would be for the GPU to not have access to the DRAM.
4. You definitely have a point about the move engines not being on this diagram but I don't see it being much of use but I do think that it's used for faster copying of data between the GPU and CPU.
5. I don't think that black line is anything but a mistake plus that interview with the architect of the xbone basically disclosed the eSRAM as nothing more than an evolution of the eDRAM so I think the GPU is the only one with the access to it.
6. I don't think there are any buses between the each of the MMU's considering the diagram doesn't show the MMU's being connected together.
