| fatslob-:O said: The truth pretty much lies in that hotchips conference slide. It honestly doesn't get any easier than this to my eyes. |
There are more questions than answers on this slide. Just a few of them:
1. Does the cpu access the ddr3 with 30GB/s max? What with the rest of the 68GB/s?
2. The memory transfer between gpu and esram is a mystery. You CANNOT transfer 109GB/s in both directions the same time with only 4 memory controllers.
3. Where are the two dma controllers of the gpu? Are they in reality the two "swizzle copy" dme engines?
4. Where are the 4 dme engines located (if two of them are not the gpu dma controllers), and to what do they connect at what possible speeds?
5. What is that thin black line between cpu and esram busses? (we now know the cpu can't access esram directly)
6. What is the speed of the bus between gpu mmu and cpu mmu? Who drives the bus?
There are other finer details that are unclear in that slide
