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drkohler said: That link "example" has me puzzled ever since I saw it. Unfortunately it leads to people falsely "adding up numbers" like you correctly mention. 1. They couldn't figure out where the four dma controllers go so they put them idle at the bottom, without showing what they connect to. The display/Scan box should be drawn connected to the esram, of course, not placed in limbo (and the video encoder likely sits there, too). 2. Read command of the gpu is shown as 4G/s. But where are they reading from? Either from esram or from dram, so these bandwidth numbers are already allocated for at all times... 3. The gpu memory controller shows 0.5G/s write + 5.5G/s "read from dram". But where are they reading from? Either from esram or dram, so these bandwidth numbers are already allocated for at all times... 4. The gpu memory controller shows 102G/s r/w to esram and 42G/s r/w to dram. If that were true, there woud be two physically separated (256bit) data and (34bit) address busses, in addition to the physically separated 37G(s data/address bus to the gpu and another 25G/s data/address bus to the Northbridge. That is one hell of a bus layout. Congrats to the hardware engineers (or more likely, this diagram is nonsense). All in all, this diagram is more puzzling than revealing.. |
I think that diagram is "guesses" based in what information the guy have from Durango.
One of the questions that I have is about the DataMoves...
The DataMove have direct bus connect to all memory (eSRAM and MainRAM)? It the point is to free up the CPU/CPU from these tasks then it needs to have access between eSRAM and MainRAM to move data without need to ask to CPU... but how that works? Because how can it move data without know what CPU or GPU is working or doing.
That's a example...
