superchunk on 16 February 2013
| DarkTemplar said: @superchunk I thought the Wii U CPU was able to rum 1 thread per core and each of them is able to fetch 2 instructions per cycle, but on the OP you said that each core is able to handle 2 threads, do you have a source for your information? Also could you detail the cache size of each core on the CPU? (And it seems that they are not shared unlike the previous information we had). Core 0: 512 kB Core 1: 2 MB Core 2: 512 kB ... Anyway, does anyone had information on what type SIMD instructions the Wii U CPU has? (I would like to read about it so I can understand better how it is possible to improve the performance of a code by properly vectorizing it for the CPU). Did Marcan say that those instructions were customized (i.e. different from the Wii CPU) but still weak when compared to the AVX set present on modern Intel processors? |
Thanks for pointing out the threads... I overlooked that in my last edit.
As for the CPU cache, here is the info from gaf thread linked in OP. We can see it has a total of 3MB L2 cache and its not per core, therefore it has to be shared. It also has 32kB + 32kB of L1 cache in the standard setup that is listed as per core. The other info may be buried in that thread, but I am not sure. I could only focus on raw specs at this point.
- 3 MB eDRAM L2 cache:
Core 0: 512 kB
Core 1: 2 MB
Core 2: 512 kB - 32 kB L1 Instruction cache
- 32 kB L1 Data Cache
- Locked L1 Data cache DMA per core
