Wii U GPU Die Image! Chipworks is AWESOME!

[HoloDust]

Aielyn said:

Lafiel said:
actually it is assumed they do 2 floating point operations(FLOPS) per clock (single precision), because all stream processors based on VLIW-5 (or VLIW-4 or GCN) architecture do so, you can read that up on amd.com (320 sps x 2 flops/clock x 550MHz = 352Gflops)

the shaders cores in the Xenos each contain 5 ALUs, which are capable of 2Flops/clock each and hence are similar to the SPs in newer designs, so you get a total of 48x5 = 240 ALUs x 2 flops/clock x 500MHz = theoretical processing power of 240Gflops

as for the power consumption I can only imagine the newer designs of the ALUs/SPs themselves are just less prone to power leakage and more simple, while maintaining the same workrate, so the chip is using less power overall and the newer organization into big blocks might get rid of bottlenecks in certain situations

I've chosen to respond to your answer, rather than HoloDust's, because it contained the most information.

Let me ask you this - how does a "stream processor" differ from an "ALU"? That is, I can understand that both have 2 flops/clock, but if that's the case, why aren't they called the same thing? What does one do that the other doesn't?

I this case, they are the same, there most likely isn't actually any difference between them - Xenos' shaders are based on R600 architecture, for WiiU it is believed it is based on R700, but Markan said it's registers are R6xx, so it might be also based on R600. Even if it's R700 (or even Evergreen) they are all VLIW5, which means 4 "simple" + 1 "special" in group (let's call them like that, to not overcomplicate things). VLIW5 was pretty inefficient, using mostly 3-4 out of 5 ALUs, so later they dropped to VLIW4, and finally to GCN in 77xx and up cards.