baka on 26 February 2007
staticneuron said:
The SPE's can have data sent to them then send the output to any device connected on the EIB or (a method a warhawk developer hinted at) drop data onto the EIB/Memory so the SPE's can process it and put it back to the EIB.
That's true, but there are still a few caveats. The fastest transfers for example would be on the CPU itself, since that's where more of the bandwidth is. Note how the data transfer rate drops in IBM's tests even between relatively distant SPUs on the bus:
http://www-128.ibm.com/developerworks/power/library/pa-cellperf/#table1
Of course, the data rate of the EIB is still faster than the RAM connected to the SPU, but this also assumes nothing else is happening on the bus. Other components, which might be under contention, would likely be slower. If the developers are running low on processing power on the primary core this might be useful, or if they're working on a large data set, but generally the small programs that would make the most use of the CPU time would run within the SPU's own RAM - which can be accessed at least twice as fast as any other RAM in the system. Finally, the primary core also needs to be aware of the SPU job's completion, or at least the existence of intermediate output data, even if it doesn't take the result directly. Polling would be inefficient, no doubt an interrupt exists for this.
