| runvist said:
|
Actually I just noticed my math was totally wrong (I interchanged PPU and SPU die size).
The die size (45nm) of an SPU is 6.47mm^2, of a PPU 11.32mm^2 The rest of the cell chip (115.46mm^2) is the EIB and some other stuff (which comes to around 50mm^2). So a 16PPU/128SPU chip needs 16*11.32 + 128*6.47 mm^2, "only" around 1000mm' 2 for the processors. Of course the EIB is a nightmare now (this is the bus that lets every processing element on the cell talk with very other processing element. With only 9 elements on the cell die, that is doable, but already requires about 40mm '2 of die surface. Now with 144 processing elements, it becomes an absolute engineering nightmare, probably impossible to do at all. So a 16PPU/128SPU supercell chip most likely would be segmented, basically 16 individual cell chips which know almost nothing of each other. Next the EIB would not scale to 16* 40mm^2 but designed to something smaller like 300mm^2 (with reduced capabilities as the consequence). You'd end up in a chip roughly 1000mm^2 (processors) + 300mm^2 (reduced EIB) + (at least) 100mm^2 (rest of the superchip, like "mechnaism for work allocation"), Still that is a >1400mm^2 in 45nm chip or around >800mm^2 in 28nm. Way too expensive to manufacture (we're probably approaching the four digit number now). And again, power requirements would be insane as well.
