runqvist said:
So it would be possible according to my math, but not likely. |
You can't shrink linearly everything on a die. particularly the cell has an element interconnect bus that is very hard to shrink (and the pad area is another more obvious example). The 100nm^2 above is a wild guess for the whole "everything else but processors" in the cell, and 100mm^2 are very generous and could be two to four times bigger). Also possible improvements in the SPUs and PPUs would further increase the sizes of those elements. Nobody is going to design such a monster. And we haven't even looked at the power draw of such a monster Even if the cell used only 25Watts, a die-shrunk chip 16 times the cell would use 250Watts at least.