drkohler on 17 November 2011
superchunk said:
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No, not at all. It basically tells you how densely you can pack transistors onto a die. Simplified, into a cell approximately the size 2*(32nm)^2, you can pack one transistor. In theory, you can pack twice as many transistors into the same area with 32nm as with 45nm, so you get twice as many dies out of your waver (and the whole things can run faster as the distances are shorter). In reality, you can't really double, because the smaller the stuff gets, the more problems you run into, requiring redesigns and "emergency measures" to get the thing runnign at all.
